| Autor: |
Wang, Huimin, Yang, Yongheng, Ge, Xinglai, Zuo, Yun, Yue, Yan, Li, Songtao |
| Předmět: |
|
| Zdroj: |
IEEE Transactions on Power Electronics; Mar2022, Vol. 37 Issue 3, p3334-3356, 23p |
| Abstrakt: |
Phase-locked loops (PLLs) and frequency-locked loops (FLLs) are of importance in power and energy applications. Both technologies have been introduced to speed-sensorless- controlled motor drives, and increasing applications of PLLs and FLLs for speed estimation are foreseen. To enable a proper and good design, a thorough review of the PLL- and FLL-based speed estimation schemes is then provided in this article. It is revealed through the review that many PLL- and FLL-based estimation schemes fail to accurately track a frequency ramp (i.e., obvious estimation errors appear), which may lead to a compromised estimation accuracy when these schemes that are applied in induction motor drives operating during acceleration and deceleration processes. To address this, the proven speed estimation schemes together with new attempts are also presented in this article. Moreover, various challenges to the PLL- and FLL-based speed estimation schemes, including harmonics, dc offsets, and parameter variations, are considered when evaluating these schemes. Solutions to tackle these disturbances are accordingly presented. In addition, two representative estimation schemes are exemplified through experimental tests. Finally, further challenges in using the PLL- and FLL-based schemes for speed estimation are discussed. [ABSTRACT FROM AUTHOR] |
| Databáze: |
Complementary Index |
| Externí odkaz: |
|
