| Autor: |
Phoon, Jun-Hoe, Lee, Wai-Kong, Wong, Denis Chee-Keong, Yap, Wun-She, Goi, Bok-Min |
| Předmět: |
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| Zdroj: |
IEEE Transactions on Very Large Scale Integration (VLSI) Systems; Dec2020, Vol. 28 Issue 12, p2672-2684, 13p |
| Abstrakt: |
Postquantum cryptography attracts a lot of attention from the research community recently due to the emergence threat from quantum computer toward the conventional cryptographic schemes. In view of that, NIST had initiated the standardization process in 2017. Bit flipping key encapsulation (BIKE) designed by Aragon et al. is one of the promising code-based schemes among the round-3 candidates. BIKE utilizes a quasi-cyclic medium density parity check (QC-MDPC) code and incorporates a few variants derived from the McEliece, Niederreiter, and Ouroboros schemes. In this article, we present efficient and constant time implementation of BIKEI and BIKE-III in field-programmable gate array (FPGA), which has the best area–time efficiency so far. We proposed modification to the original one-round bit flipping algorithm to achieve more area–time-efficient decoding in hardware, which achieved latency of 464.73 and $556.52~\mu \text{s}$ for BIKE-I and BIKE-III, respectively, in Virtex-7. A pipelined key encapsulation architecture is proposed to speedup the key encapsulation of BIKE-I and BIKE-III, achieving the latency of 146.47 and $153.25~\mu \text{s}$ on the same FPGA platform. Considering the Artix-7 FPGA platform, our combined key generation and encapsulation module for BIKE-I is also three more area–time efficient compared with the state-of-the-art BIKE-I implementation by Aragon et al. [ABSTRACT FROM AUTHOR] |
| Databáze: |
Complementary Index |
| Externí odkaz: |
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