| Autor: |
Sun, Xun, Rahman, Fahim ur, Pamula, Venkata Rajesh, Kim, Sung, Li, Xi, John, Naveen, Sathe, Visvesh S. |
| Předmět: |
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| Zdroj: |
IEEE Journal of Solid-State Circuits; Nov2019, Vol. 54 Issue 11, p3215-3225, 11p |
| Abstrakt: |
Traditional digital systems employ independent loops to control supply voltage (${\mathit {V}}_{\text {dd}}$) and clock frequency ($f_{\text {clk}}$). A clock regulation loop, for instance, a phase-locked loop (PLL), locks the system clock to a reference clock (REFCLK). Concurrently, a voltage regulation loop sets ${\mathit {V}}_{\text {dd}}$ to a target value under rapidly varying load current or line-side disturbances. Limitations in voltage regulator loop bandwidth result in significant ${\mathit {V}}_{\text {dd}}$ fluctuation, leading to timing slack degradation in digital voltage domains. Maintaining timing slack in the presence of supply noise or temperature (T) variation incurs energy-wasteful ${\mathit {V}}_{\text {dd}}$ guardbands. In this article, we present a unified clock and power (UniCaP) architecture that instantaneously adapts $f_{\text {clk}}$ to ${\mathit {V}}_{\text {dd}}$ and $T$ variations, requiring minimal guardbands. UniCaP absorbs ${\mathit {V}}_{\text {dd}}$ control into the clock regulation loop, using it to adjust $f_{\text {clk}}$ and lock system clock to REFCLK. UniCaP enables all-digital construction with aggressive ${\mathit {V}}_{\text {dd}}$ guardband reduction and the capability for on-the-fly dynamic voltage and frequency scaling (DVFS) events. We deployed the UniCaP architecture on a 65-nm buck converter test chip powering a 0.6–1.0-V Cortex-M0 microprocessor with autonomous transition between continuous and discontinuous conduction modes (CCM/DCM) in order to support a wide load current range. The UniCaP test chip demonstrates 82% average ${\mathit {V}}_{\text {dd}}$ guardband reduction, without any performance loss from adaptive clocking, and temperature margin reductions of 40–55 mV. [ABSTRACT FROM AUTHOR] |
| Databáze: |
Complementary Index |
| Externí odkaz: |
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