| Autor: |
Ganapathy, Shrikanth, Kalamatianos, John, Kasprak, Keith, Raasch, Steven |
| Předmět: |
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| Zdroj: |
DAC: Annual ACM/IEEE Design Automation Conference; 2017, Issue 54, p613-618, 6p |
| Abstrakt: |
Adoption of near-threshold voltage (NTV) operation in SRAMbased memories has been limited by reduced robustness resulting from marginal transistor operation that results in bit failures. Using silicon measurements from a large sample of 14nm FinFET test chips, we show that our cells operate at frequencies of up to 1GHz with a minimum 15% voltage guardband, below which the cells begin to fail. We find that when operated at 32.5% below nominal voltage, >95% of the lines experience fewer than 2 failures, which can be corrected with SECDED ECC. Our results indicate that for frequencies of up to 1GHz, NTV can help maximize power savings potential while requiring minimal protection. [ABSTRACT FROM AUTHOR] |
| Databáze: |
Complementary Index |
| Externí odkaz: |
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