Reliability aging and modeling of chip-package interaction on logic technologies featuring high-k metal gate planar and FinFET transistors.
| Autor: | Lee, Jen-Hao, Chen, Eliot S.H., Lee, Yung-Huei, Lin, Chun-Hung, Wu, Chun-Yu, Hsieh, Ming-Han, Huang, Kevin, Wang, Jhong-Sheng, Tsai, Yung-Sheng, Lu, Ryan, Shih, Jiaw-Ren |
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| Zdroj: | 2015 IEEE International Integrated Reliability Workshop (IIRW); 2015, p63-67, 5p |
| Databáze: | Complementary Index |
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