Enabling pre-assembly process of 3D wafers with high topography at the backside.
| Autor: | Podpod, A., Demeurisse, C., Inoue, F., Duval, F., Visker, J., De Vos, J., Rebibis, K., Miller, R. A., Beyer, G., Beyne, E. |
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| Zdroj: | 2015 IEEE 17th Electronics Packaging & Technology Conference (EPTC); 1/1/2015, p1-5, 5p |
| Databáze: | Complementary Index |
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