| Autor: |
Yasue, Toshio, Kitamura, Kazuya, Watabe, Toshihisa, Shimamoto, Hiroshi, Kosugi, Tomohiko, Watanabe, Takashi, Aoyama, Satoshi, Monoi, Makoto, Wei, Zhiheng, Kawahito, Shoji |
| Předmět: |
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| Zdroj: |
IEEE Transactions on Electron Devices; Jan2016, Vol. 63 Issue 1, p153-161, 9p |
| Abstrakt: |
A 1.7-in, 33-Mpixel, 120-frames/s, 14-bit CMOS image sensor has been developed. The 7936 (H) \times \,\, 4412 (V) pixel CMOS image sensor, which uses 14-b depletion-mode MOS (DMOS) capacitor-based two-stage cyclic A/D converters (ADCs) and 64 parallel scalable low-voltage signaling output ports, operates at a data rate of 63.8 Gb/s. DMOS capacitors have a high capacitance density, but it is difficult to achieve high bit resolutions in ADCs with these capacitors because their capacitance depends on the applied voltage. Column-parallel two-stage cyclic ADCs overcome this difficulty using a split-sampling DMOS capacitors architecture. The two-stage cyclic ADC with the DMOS capacitors at a 6.4- \mu \text{m} column pitch exhibited a differential nonlinearity of 0.95/−0.80 least significant bit (LSB); the integral nonlinearity was 2.57/−28.27 LSB at a 14-b resolution. The CMOS image sensor implemented with a 90-/65-nm technology exhibited a sensitivity of 5.22 V/lx \,\cdot \, \text{s}$ and a random noise of 3.6 \text{e}^{-}_{\mathrm {rms}} with a gain of 3.3 at 120 frames/s while dissipating 3.2 W. [ABSTRACT FROM AUTHOR] |
| Databáze: |
Complementary Index |
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