| Autor: |
Rad RE; Department of Electrical and Computer Engineering, Sungkyunkwan University, Suwon 16419, Korea.; SKAIChips Co., Ltd., Suwon 16419, Korea., Kim S; Department of Electrical and Computer Engineering, Sungkyunkwan University, Suwon 16419, Korea.; SKAIChips Co., Ltd., Suwon 16419, Korea., Pu Y; Department of Electrical and Computer Engineering, Sungkyunkwan University, Suwon 16419, Korea.; SKAIChips Co., Ltd., Suwon 16419, Korea., Jung Y; Department of Electrical and Computer Engineering, Sungkyunkwan University, Suwon 16419, Korea.; SKAIChips Co., Ltd., Suwon 16419, Korea., Huh H; Department of Electrical and Computer Engineering, Sungkyunkwan University, Suwon 16419, Korea.; SKAIChips Co., Ltd., Suwon 16419, Korea., Yoo J; Department of Electrical and Computer Engineering, Sungkyunkwan University, Suwon 16419, Korea.; SKAIChips Co., Ltd., Suwon 16419, Korea., Kim S; Department of Electrical and Computer Engineering, Sungkyunkwan University, Suwon 16419, Korea.; SKAIChips Co., Ltd., Suwon 16419, Korea., Lee KY; Department of Electrical and Computer Engineering, Sungkyunkwan University, Suwon 16419, Korea.; SKAIChips Co., Ltd., Suwon 16419, Korea. |
| Abstrakt: |
This paper presents a digital power amplifier (DPA) with a 43-dB dynamic range and 0.5-dB/step gain steps for a narrow-band Internet of Things (NBIoT) transceiver application. The proposed DPA is implemented in a dual-band architecture for both the low band and high band of the frequency coverage in an NBIoT application. The proposed DPA is implemented in two individual paths, power amplification, and power attenuation, to provide a wide range when both paths are implemented. To perform the fine control over the gain steps, ten fully differential cascode power amplifier cores, in parallel with a binary sizing, are used to amplify power and enable signals and provide fine gain steps. For the attenuation path, ten steps of attenuated signal level are provided which are controlled with ten power cores, similar to the power amplification path in parallel but with a fixed, small size for the cores. The proposed implementation is finalized with output custom-made baluns at the output. The technique of using parallel controlled cores provides a fine power adjustability by using a small area on the die where the NBIoT is fabricated in a 65-nm CMOS technology. Experimental results show a dynamic range of 47 dB with 0.5-dB fine steps are also available. |
