| Autor: |
Yoon YJ, Eun HR, Seo JH, Kang HS, Lee SM, Lee J, Cho S, Tae HS, Lee JH, Kang IM |
| Jazyk: |
angličtina |
| Zdroj: |
Journal of nanoscience and nanotechnology [J Nanosci Nanotechnol] 2015 Oct; Vol. 15 (10), pp. 7430-5. |
| DOI: |
10.1166/jnn.2015.11146 |
| Abstrakt: |
We have investigated and proposed a highly scaled tunneling field-effect transistor (TFET) based on Ge/GaAs heterojunction with a drain overlap to suppress drain-induced barrier thinning (DIBT) and improve low-power (LP) performance. The highly scaled TFET with a drain overlap achieves lower leakage tunneling current because of the decrease in tunneling events between the source and drain, whereas a typical short-channel TFET suffers from a great deal of tunneling leakage current due to the DIBT at the off-state. However, the drain overlap inevitably increases the gate-to-drain capacitance (Cgd) because of the increase in the overlap capacitance (Cov) and inversion capacitance (Cinv). Thus, in this work, a dual-metal gate structure is additionally applied along with the drain overlap. The current performance and the total gate capacitance (Cgg) of the device with a dual-metal gate can be possibly controlled by adjusting the metal gate workfunction (φgate) and φoverlap-gate in the overlapping regions. As a result, the intrinsic delay time (τ) is greatly reduced by obtaining lower Cgg divided by the on-state current (Ion), i.e., Cgg/Ion. We have successfully demonstrated excellent LP and high-speed performance of a highly scaled TFET by adopting both drain overlap and dual-metal gate with DIBT minimization. |
| Databáze: |
MEDLINE |
| Externí odkaz: |
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