Robust DC and efficient time-domain fast fault simulation

Autor: J.J. Dohmen, Wil H. A. Schilders, Tgj Theo Beelen, Bratislav Tasić, van M Beurden, E.J.W. ter Maten, de A Vries

Publikováno v: COMPEL: The International Journal for Computation and Mathematics in Electrical and Electronic Engineering, 33(4), 1161-1174. Emerald Group Publishing Ltd.

Purpose – Imperfections in manufacturing processes may cause unwanted connections (faults) that are added to the nominal, “golden”, design of an electronic circuit. By fault simulation one simulates all situations. Normally this leads to a larg

Externí odkaz: https://explore.openaire.eu/search/publication?articleId=doi_dedup___::66aa104e071d8b3d81097b30eaf60ea7
https://doi.org/10.1108/compel-12-2012-0364