Zobrazeno 1 - 10
of 969
pro vyhledávání: '"systolic arrays"'
Publikováno v:
In Journal of Systems Architecture October 2024 155
Autor:
Atef Ibrahim
Publikováno v:
Ain Shams Engineering Journal, Vol 14, Iss 10, Pp 102188- (2023)
Security and privacy issues with Internet of Things (IoT) network make it difficult to use IoT technology. Cryptographic protocols can be put in place on IoT edge nodes to address security flaws. Since the edge nodes have few resources, it is challen
Externí odkaz:
https://doaj.org/article/e238acf5100e4df4a71b0c3372c71be2
Autor:
Atef Ibrahim
Publikováno v:
Egyptian Informatics Journal, Vol 23, Iss 2, Pp 239-245 (2022)
This paper presents a combined two-dimensional word-based serial-in/serial-out systolic processor for field multiplication and squaring over GF(2m) to improve hardware utilization and power consumption. The proposed processor is extracted by applying
Externí odkaz:
https://doaj.org/article/9f46e18eb2cb427f9f9e15c6ce9d6806
Autor:
Shalini Shanmugam, Selvathi Dharmar
Publikováno v:
IET Circuits, Devices and Systems, Vol 16, Iss 1, Pp 1-12 (2022)
Abstract Epilepsy is one of the most common neurological disorders; it affects millions of people globally. Because of the risks to health that it causes, the study and analysis of epilepsy have been given considerable attention in the biomedical fie
Externí odkaz:
https://doaj.org/article/9ed66f7132a74afba0d058de9a7d91e9
Autor:
Doru Florin Chiper, Arcadie Cracan
Publikováno v:
Sensors, Vol 23, Iss 13, p 6220 (2023)
In this paper, we present two systolic array algorithms for efficient Very-Large-Scale Integration (VLSI) implementations of the 1-D Modified Discrete Sine Transform (MDST) using the systolic array architectural paradigm. The new algorithms decompose
Externí odkaz:
https://doaj.org/article/da25daef60674b7fa898c3d0c6b6c26c
Autor:
Doru Florin Chiper, Arcadie Cracan
Publikováno v:
Applied Sciences, Vol 13, Iss 12, p 6927 (2023)
In this paper, we propose a new hardware algorithm for an integer based discrete cosine transform (IntDCT) that was designed to allow an efficient VLSI implementation of the discrete cosine transform using the systolic array architectural paradigm. T
Externí odkaz:
https://doaj.org/article/0b1acae6885c4d47a8bf0e46a7310388
Publikováno v:
IET Circuits, Devices and Systems, Vol 15, Iss 2, Pp 94-103 (2021)
Abstract Next‐generation sequencing techniques have dramatically increased the amount of genomic data being sequenced, which calls for the acceleration of the alignment algorithms. This article proposes an FPGA‐based accelerated implementation of
Externí odkaz:
https://doaj.org/article/a67079016d8c4276b56a040cf1e13794
Autor:
Atef Ibrahim
Publikováno v:
Alexandria Engineering Journal, Vol 60, Iss 1, Pp 1379-1388 (2021)
This paper exhibits a word-serial unified and scalable semi-systolic processor core for concurrently executing both multiplication and squaring operations over GF(2k). The processor is extracted by applying a chosen non-linear scheduling and projecti
Externí odkaz:
https://doaj.org/article/4ba278e38cac49498483698a23532267
Publikováno v:
IEEE Access, Vol 9, Pp 96700-96710 (2021)
The application diversity and evolution of AI accelerator architectures require innovative DFT solutions to address issues such as test time, test power, performance and area overhead. Full scan DFT, because of its enhanced controllability and observ
Externí odkaz:
https://doaj.org/article/4c17aae9c20640678c7c6ef41f7be6eb
Autor:
Kashif Inayat, Fahad Bin Muslim, Javed Iqbal, Syed Agha Hassnain Mohsan, Hend Khalid Alkahtani, Samih M. Mostafa
Publikováno v:
Sensors, Vol 23, Iss 9, p 4297 (2023)
Systolic arrays are an integral part of many modern machine learning (ML) accelerators due to their efficiency in performing matrix multiplication that is a key primitive in modern ML models. Current state-of-the-art in systolic array-based accelerat
Externí odkaz:
https://doaj.org/article/08d33caba7b34af6bed254b2a03a9e9f