Zobrazeno 1 - 10
of 1 761
pro vyhledávání: '"synchronous circuit"'
Publikováno v:
Discrete Event Dynamic Systems
Discrete Event Dynamic Systems, 2023, 33, ⟨10.1007/s10626-022-00371-7⟩
Discrete Event Dynamic Systems, 2023, 33, ⟨10.1007/s10626-022-00371-7⟩
International audience; A fundamental step in circuit design is the placement of pipeline stages, which can drastically increase the data throughput. Retiming allows optimizing the pipeline with regard to a criterion, for example the required number
Externí odkaz:
https://explore.openaire.eu/search/publication?articleId=doi_dedup___::029ec32eee91fba3263c3f22dc8eb288
https://hal.science/hal-03952519
https://hal.science/hal-03952519
Akademický článek
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Akademický článek
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Publikováno v:
MWSCAS
We explore the use of dependent types to address the disparity between the theory and the practical hardware description of DSP circuits. After discussing an approach to modeling synchronous circuit behaviour in Idris (a pure functional language with
Externí odkaz:
https://explore.openaire.eu/search/publication?articleId=doi_dedup___::e46ceb4ae1351ae8bf08ac9b25d764c3
https://doi.org/10.1109/mwscas47672.2021.9531730
https://doi.org/10.1109/mwscas47672.2021.9531730
Design of the Multiple Synchronous Paralleling System of Pumped Storage Unit for Offshore Wind Power
Publikováno v:
2021 IEEE International Conference on Power, Intelligent Computing and Systems (ICPICS).
Analysis the necessity of supporting construction of offshore wind power and pumped storage power station, and the design of multiple synchronous paralleling system of unit. Describes the shortcomings of the traditional design of the synchronous circ
Externí odkaz:
https://explore.openaire.eu/search/publication?articleId=doi_________::25eed4023fcae93ba59eb89bbb5f8a55
https://doi.org/10.1109/icpics52425.2021.9524234
https://doi.org/10.1109/icpics52425.2021.9524234
Publikováno v:
Application and Theory of Petri Nets and Concurrency
42nd International Conference on Application and Theory of Petri Nets and Concurrency
42nd International Conference on Application and Theory of Petri Nets and Concurrency, Jun 2021, Paris, France. pp.55-75, ⟨10.1007/978-3-030-76983-3_4⟩
Application and Theory of Petri Nets and Concurrency ISBN: 9783030769826
Petri Nets
42nd International Conference on Application and Theory of Petri Nets and Concurrency
42nd International Conference on Application and Theory of Petri Nets and Concurrency, Jun 2021, Paris, France. pp.55-75, ⟨10.1007/978-3-030-76983-3_4⟩
Application and Theory of Petri Nets and Concurrency ISBN: 9783030769826
Petri Nets
International audience; This paper introduces an extension of Timed Petri Nets for the modeling of synchronous electronic circuits, addressing pipeline design problems. Petri Nets have been widely used for the modeling of electronic circuits. In part
Externí odkaz:
https://explore.openaire.eu/search/publication?articleId=doi_dedup___::06d8dd580bf5a190e0bee1b2bd34a7c7
https://hal.archives-ouvertes.fr/hal-03266806
https://hal.archives-ouvertes.fr/hal-03266806
Publikováno v:
2021 IEEE 28th Symposium on Computer Arithmetic (ARITH)
2021 IEEE 28th Symposium on Computer Arithmetic (ARITH), Jun 2021, Lyngby, Denmark. pp.37-44, ⟨10.1109/ARITH51176.2021.00018⟩
ARITH
2021 IEEE 28th Symposium on Computer Arithmetic (ARITH), Jun 2021, Lyngby, Denmark. pp.37-44, ⟨10.1109/ARITH51176.2021.00018⟩
ARITH
International audience; A major step in arithmetic operators design is the placement of pipeline stages, with the goal of drastically increase the data throughput. Approaches, such as the as-soon-as-possible greedy algorithm, allow pipelining with a
Externí odkaz:
https://explore.openaire.eu/search/publication?articleId=doi_dedup___::2fbfe78a62d55cd4b3fb25038edee80d
https://hal.archives-ouvertes.fr/hal-03464317/file/Arith2021.pdf
https://hal.archives-ouvertes.fr/hal-03464317/file/Arith2021.pdf
Autor:
Huichu Liu, Tanay Karnik, Morris Daniel H, Kaushik Vaidyanathan, Dmitri E. Nikonov, Sasikanth Manipatruni, Ian A. Young
Publikováno v:
IEEE Journal on Exploratory Solid-State Computational Devices and Circuits. 5:1-9
The supply voltage scaling has become increasingly challenging in the advanced CMOS technology due to the threshold voltage requirement for transistor OFF leakage, limiting the system energy efficiency. Spintronic logic utilizes the physical quantity
Externí odkaz:
https://explore.openaire.eu/search/publication?articleId=doi_________::659d70b04ecb7cd22bea868f2d106ce7
https://doi.org/10.1109/jxcdc.2019.2897598
https://doi.org/10.1109/jxcdc.2019.2897598
Autor:
P. Rajasekar, C. S. Subash Kumar
Publikováno v:
Wireless Personal Communications. 107:2231-2245
Todays, transistor level design plays major impact in the power consumption of the VLSI based design. The various logic design models are used to reduce the power consumption that includes synchronous and asynchronous design model. The operation of s
Externí odkaz:
https://explore.openaire.eu/search/publication?articleId=doi_________::deae77c22e5a49b6398587d5d8846bde
https://doi.org/10.1007/s11277-019-06380-4
https://doi.org/10.1007/s11277-019-06380-4
Publikováno v:
Procedia Computer Science. 155:815-821
Line loss, as one of the most important economic indicator to evaluate the quality of the power distribution network, the importance of monitoring it is self-evident. A new method is presented to calculate the line loss, which can consider the three-
Externí odkaz:
https://explore.openaire.eu/search/publication?articleId=doi_________::80e136c3989f729706654336613eda6e
https://doi.org/10.1016/j.procs.2019.08.120
https://doi.org/10.1016/j.procs.2019.08.120