Zobrazeno 1 - 10
of 379
pro vyhledávání: '"statistical static timing analysis"'
Akademický článek
Tento výsledek nelze pro nepřihlášené uživatele zobrazit.
K zobrazení výsledku je třeba se přihlásit.
K zobrazení výsledku je třeba se přihlásit.
Publikováno v:
IEEE Access, Vol 8, Pp 197194-197202 (2020)
In the advanced technology nodes, process parameter variations are increasingly resulting in unpredictable device behavior. The issue is even aggravated by low power requirements which stretches the transistor operation into near-threshold regime. De
Externí odkaz:
https://doaj.org/article/78477dad39fe42629028d4c4c7066896
Autor:
S. R. Ramesh, R. Jayaparvathy
Publikováno v:
Automatika, Vol 60, Iss 3, Pp 360-367 (2019)
Advances in the VLSI process technology lead to variations in the process parameters. These process variations severely affect the delay computation of a digital circuit. Under such variations, the various delays, i.e. net delay, gate delay, etc., ar
Externí odkaz:
https://doaj.org/article/a1b274e3d2ad4aa9a0eae4bf99e18be5
Akademický článek
Tento výsledek nelze pro nepřihlášené uživatele zobrazit.
K zobrazení výsledku je třeba se přihlásit.
K zobrazení výsledku je třeba se přihlásit.
Publikováno v:
IEEE Transactions on Applied Superconductivity. 30:1-12
Superconducting single flux quantum (SFQ) technology is an ultra-high performance and low power technology. The technology, however, lacks many of the design automation tools and capabilities that are commonplace in CMOS technology. This article desc
Autor:
Yuanyuan Zhang, Saralees Nadarajah
Publikováno v:
Wireless Personal Communications. 116:1593-1612
Statistical static timing analysis involves the distributions of the maximum and minimum of correlated random variables. Nadarajah and Kotz (IEEE Trans Very Large Scale Integr Syst 16:210–2012, 2008) derived closed form expressions for the distribu
Autor:
Mishagli, Dmytro, Blokhina, Elena
Publikováno v:
Computational Science – ICCS 2020
In this paper, we discuss methods for determining delay distributions in modern Very Large Scale Integration design. The delays have a non-Gaussian nature, which is a challenging task to solve and is a stumbling block for many approaches. The problem
Autor:
Feng, Zhuo
As IC technologies scale to the nanometer regime, efficient and accurate modeling and analysis of VLSI systems with billions of transistors and interconnects becomes increasingly critical and difficult. VLSI systems impacted by the increasingly high
Externí odkaz:
http://hdl.handle.net/1969.1/ETD-TAMU-2009-12-7142
Publikováno v:
MWSCAS
Although statistical methods have been widely used in static timing analysis of circuits, there are still challenges to cope with including high process variations in circuits. Due to high process variations, random variables like delay may not follo
Autor:
Kim, Hyun Sung
As semiconductor technology is scaled and voltage level is reduced, the impact of the variation in power supply has become very significant in predicting the realistic worst-case delays in integrated circuits. The analysis of power supply noise is in
Externí odkaz:
http://hdl.handle.net/1969.1/ETD-TAMU-1902