Výsledky vyhledávání - "negative bit line"

Akademický článek

Tento výsledek nelze pro nepřihlášené uživatele zobrazit.
K zobrazení výsledku je třeba se přihlásit.

Design and Analysis of SRAM Cell using Negative Bit-Line Write Assist Technique and Separate Read Port for High-Speed Applications

Autor: Jitendra Kumar Mishra, Kavindra Kandpal, Lakshmi Likhitha Mankali, Manish Goswami, Prasanna Kumar Misra

Publikováno v: Journal of Circuits, Systems and Computers. 30

The present day electronic gadgets have semiconductor memory devices to store data. The static random access memory (SRAM) is a volatile memory, often preferred over dynamic random access memory (DRAM) due to higher speed and lower power dissipation.

Externí odkaz: https://explore.openaire.eu/search/publication?articleId=doi_________::d35153ba385251e106384aaab574c0eb
https://doi.org/10.1142/s0218126621502704

Zobrazit plný text záznamu

A novel 8T SRAM with improved cell density

Autor: B. Naresh Kumar Reddy, Ch. Ramalingaswamy, Dharavath Ramesh, R. Nagulapalli

Publikováno v: Analog Integrated Circuits and Signal Processing. 98:357-366

Low voltage and high-density SRAM memory creates new challenges such as stability and sense margin. Conventional decoupled 8T SRAM cell has improved read stability but small sense margin and high leakage power which makes it unsuitable for small supp

Externí odkaz: https://explore.openaire.eu/search/publication?articleId=doi_________::9906fbc8de4a22652ed8f00925e3b199
https://doi.org/10.1007/s10470-018-1309-z

Zobrazit plný text záznamu

Akademický článek

Tento výsledek nelze pro nepřihlášené uživatele zobrazit.
K zobrazení výsledku je třeba se přihlásit.

Offset-Compensated Cross-Coupled PFET Bit-Line Conditioning and Selective Negative Bit-Line Write Assist for High-Density Low-Power SRAM

Autor: Seong-Ook Jung, Hanwool Jeong, Taejoong Song, Tae-Won Kim, Younghwi Yang, Gyu-Hong Kim, Hyo-sig Won

Publikováno v: IEEE Transactions on Circuits and Systems I: Regular Papers. :1-9

An offset-compensated cross-coupled PFET bit-line (BL) conditioning circuit (OC-CPBC) and a selective negative BL write-assist circuit (SNBL-WA) are proposed for high-density FinFET static RAM (SRAM). The word-line (WL) underdrive read-assist and the

Externí odkaz: https://explore.openaire.eu/search/publication?articleId=doi_________::6849811a3e48516882a0b2ac59b6cf7b
https://doi.org/10.1109/tcsi.2015.2388837

Zobrazit plný text záznamu

A 16nm dual-port SRAM with partial suppressed word-line, dummy read recovery and negative bit-line circuitries for low VMIN applications

Autor: Jhon-Jhy Liaw, Ching-Wei Wu, Yen-Huei Chen, Jonathan Chang, Wei Min Chan, Kao-Cheng Lin, Hung-jen Liao

Publikováno v: VLSI Circuits

A total solution for 8T dual-port (DP) SRAM to improve its operating voltage range (V MIN /V MAX ) is proposed. Partial suppressed word-line (PSWL) technique improves the static noise margin (SNM) when both ports (A, B ports) access at the same time.

Externí odkaz: https://explore.openaire.eu/search/publication?articleId=doi_________::f1ab970c6d1aff994de80e17fa4b98af
https://doi.org/10.1109/vlsic.2016.7573459

Zobrazit plný text záznamu

A 0.33-V, 500-kHz, 3.94-$\mu\hbox{W}$ 40-nm 72-Kb 9T Subthreshold SRAM With Ripple Bit-Line Structure and Negative Bit-Line Write-Assist

Autor: Ching-Te Chuang, Yung-Shin Kao, Ya-Ping Wu, Huan-Shun Huang, Shyh-Jye Jou, Wei Hwang, Chien-Yu Lu, Ming-Hsien Tu, Yuh-Jiun Lin, Hao-I Yang, Kuen-Di Lee

Publikováno v: IEEE Transactions on Circuits and Systems II: Express Briefs. 59:863-867

This paper presents an ultra-low-power 72-Kb 9T static random-access memory (SRAM) with a ripple bit-line (RPBL) structure and negative bit-line (NBL) write-assist. The RPBL scheme provides over 40% read access performance improvement for VDD below 0

Externí odkaz: https://explore.openaire.eu/search/publication?articleId=doi_________::59c2a971d2c5d63e493c84ad8901fcee
https://doi.org/10.1109/tcsii.2012.2231017

Zobrazit plný text záznamu

RAPIDO Testing of Assisted Write and Read operations for SRAMs

Autor: Nguyen, J., Turgis, D., Bonciani, D., Lhomme, B., Carminati, Y., Callen, O., Guirleo, G., Ciampolini, L., Ghibaudo, G.

Lowering the supply voltage of Static Random-Access Memories (SRAM) is key to reduce power consumption, however since this badly affects the circuit performances, it might lead to various forms of loss of functionality. In this work, we present silic

Externí odkaz: https://explore.openaire.eu/search/publication?articleId=dedup_wf_001::3b781907d22beed0ea93344785637ec3
https://kluedo.ub.rptu.de/frontdoor/index/index/docId/4329

Zobrazit plný text záznamu

Akademický článek

Tento výsledek nelze pro nepřihlášené uživatele zobrazit.
K zobrazení výsledku je třeba se přihlásit.

Dissertation/ Thesis

Read/write assist circuits and SRAM design

Autor: Nguyen, Quocdat Tai

This report discusses the design of read/write assist circuits which are used in a SRAM cell’s design to overcome the cell’s variations. It also explains the variability problems in a SRAM bit-cell and many approaches to address them. The basic o

Externí odkaz: http://hdl.handle.net/2152/ETD-UT-2009-12-692

Zobrazit plný text záznamu

Vyhledávací nástroje:

Upřesnit hledání