Zobrazeno 1 - 10
of 76
pro vyhledávání: '"mealy fsm"'
Publikováno v:
International Journal of Applied Mathematics and Computer Science, Vol 34, Iss 1, Pp 167-178 (2024)
In many digital systems, various sequential blocks are used. This paper is devoted to the case where the model of a Mealy finite state machine (FSM) represents the behaviour of a sequential block. The chip area occupied by an FSM circuit is one of th
Externí odkaz:
https://doaj.org/article/2154bca1a41b4c008d8b929f5ab6a1d9
Publikováno v:
IEEE Access, Vol 12, Pp 42369-42384 (2024)
A method is proposed for reducing chip area occupied by logic circuits of FPGA-based Mealy finite state machines (FSMs). The proposed method aims at optimization of FSM circuits implemented with look-up table (LUT) elements of FPGA chip. The proposed
Externí odkaz:
https://doaj.org/article/cec382d47bd24ab092148834af5321ac
Publikováno v:
International Journal of Applied Mathematics and Computer Science, Vol 32, Iss 3, Pp 479-494 (2022)
A method is proposed which aims at reducing the number of LUTs in the circuits of FPGA-based Mealy finite state machines (FSMs) with transformation of collections of outputs into state codes. The reduction is achieved due to the use of two-component
Externí odkaz:
https://doaj.org/article/f091f5a9df254d51b501f3e1ae4b38da
Publikováno v:
IEEE Access, Vol 10, Pp 36152-36165 (2022)
Practically, any digital system includes sequential blocks. This paper considers a case when LUT-based sequential blocks are represented by Mealy finite state machines (FSMs). The LUT count is one of the most important characteristics of an FSM circu
Externí odkaz:
https://doaj.org/article/aed6072abbf043e19d3b29bfdbb14b8d
Publikováno v:
Applied Sciences, Vol 13, Iss 18, p 10200 (2023)
This work proposes a method for hardware reduction in circuits of Mealy finite state machines (FSMs). The circuits are implemented as networks of interconnected look-up table (LUT) elements. The FSMs with twofold state assignment and encoding of outp
Externí odkaz:
https://doaj.org/article/6cbb8e7f60584ed0b5f715218f462082
Publikováno v:
International Journal of Applied Mathematics and Computer Science, Vol 30, Iss 4, Pp 745-759 (2020)
Practically, any digital system includes sequential blocks represented using a model of finite state machine (FSM). It is very important to improve such FSM characteristics as the number of logic elements used, operating frequency and consumed energy
Externí odkaz:
https://doaj.org/article/fdd4cf2f5b9f4b4c8961e579e84285cb
Akademický článek
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Publikováno v:
Applied Sciences, Vol 12, Iss 16, p 8065 (2022)
The main contribution of this paper is a novel design method reducing the number of look-up table (LUT) elements in the circuits of three-block Mealy finite-state machines (FSMs). The proposed method is based on using codes of collections of outputs
Externí odkaz:
https://doaj.org/article/b4edec2ef5484df2a2faf21ca2420b55
Publikováno v:
Bulletin of the Polish Academy of Sciences: Technical Sciences, Vol 69, Iss 2 (2021)
Very often, a digital system includes sequential blocks which can be represented using a model of the finite state machine (FSM). It is very important to improve such FSM characteristics as the number of used logic elements, operating frequency and c
Externí odkaz:
https://doaj.org/article/54495ed035d44696aa030307d5788c6d
Publikováno v:
Energies, Vol 15, Iss 7, p 2636 (2022)
A method is proposed for optimizing circuits of sequential devices which are used in cyber-physical systems (CPSs) implemented using field programmable gate arrays (FPGAs). The optimizing hardware is a very important problem connected with implementi
Externí odkaz:
https://doaj.org/article/c49d9b0a2f094b9bbbc84a0ef230f49a