Zobrazeno 1 - 10
of 509
pro vyhledávání: '"instructions per cycle"'
Autor:
Satwik Kundu, Rupshali Roy, M. Saifur Rahman, Suryansh Upadhyay, Rasit Onur Topaloglu, Suzanne E. Mohney, Shengxi Huang, Swaroop Ghosh
Publikováno v:
Journal of Low Power Electronics and Applications, Vol 13, Iss 1, p 16 (2023)
The size of transistors has drastically reduced over the years. Interconnects have likewise also been scaled down. Today, conventional copper (Cu)-based interconnects face a significant impediment to further scaling since their electrical conductivit
Externí odkaz:
https://doaj.org/article/5dd013fd09784b319cc59f318ba8b69b
Autor:
Farid Uddin Ahmed, Swaroop Ghosh, Asmit De, Karthikeyan Nagarajan, Masud H. Chowdhury, Mohammad Nasim Imtiaz Khan
Publikováno v:
IEEE Transactions on Very Large Scale Integration (VLSI) Systems. 29:1518-1528
Emerging nonvolatile memories (NVMs), such as resistive RAM (RRAM) and spin-transfer-torque RAM (STTRAM), present exciting opportunities for data storage applications and offer improved access speeds, retention times, power consumption, and scalabili
Externí odkaz:
https://explore.openaire.eu/search/publication?articleId=doi_________::429ab554bfe54dee880ba9bd6c6fb6a9
https://doi.org/10.1109/tvlsi.2021.3087734
https://doi.org/10.1109/tvlsi.2021.3087734
Akademický článek
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Publikováno v:
IEICE Transactions on Information and Systems. :2494-2503
RISC-V is a RISC based open and loyalty free instruction set architecture which has been developed since 2010, and can be used for cost-effective soft processors on FPGAs. The basic 32-bit integer instruction set in RISC-V is defined as RV32I, which
Externí odkaz:
https://explore.openaire.eu/search/publication?articleId=doi_dedup___::f91ce845ca4792eddf65adc9eab8f1ca
https://doi.org/10.1587/transinf.2020pap0015
https://doi.org/10.1587/transinf.2020pap0015
Publikováno v:
IEEE Access, Vol 8, Pp 172996-173007 (2020)
This study describes the design and implementation of a 256-bit very long instruction word (VLIW) microprocessor based on the new RISC-V instruction set architecture (ISA). Base integer RV32I and extension instruction sets, including RV32M, RV32F, an
Externí odkaz:
https://explore.openaire.eu/search/publication?articleId=doi_dedup___::87e0d0f342fa82e2fb83841595f0dd1a
https://doi.org/10.1109/access.2020.3024851
https://doi.org/10.1109/access.2020.3024851
Autor:
Aayush K. Chaudhary, Rohit Singh, Anirudh Seshadri, Chanchal Kumar, Eric Rotenberg, Shubham Bhawalkar
Publikováno v:
MICRO
Microarchitectural enhancements that improve performance generally, across many workloads, are favored in superscalar processor design. Targeting general performance is necessary but it also constrains some microarchitecture innovation. We explore re
Externí odkaz:
https://explore.openaire.eu/search/publication?articleId=doi_________::0fd14b99a315644ae77309b330106c8b
https://doi.org/10.1145/3466752.3480119
https://doi.org/10.1145/3466752.3480119
Autor:
Loïc Pottier, Silvina Caíno-Lores, Michela Taufer, Rafael Ferreira da Silva, Ewa Deelman, Tu Mai Anh Do
Publikováno v:
ICPP Workshops
Scientific breakthroughs in biomolecular methods and improvements in hardware technology have shifted from a single long-running simulation to a large set of shorter simulations running simultaneously, called an ensemble. In an ensemble, each indepen
Externí odkaz:
https://explore.openaire.eu/search/publication?articleId=doi_________::2210e2ac484cf450846956e790666c45
https://doi.org/10.1145/3458744.3474051
https://doi.org/10.1145/3458744.3474051
Publikováno v:
Journal of Circuits, Systems and Computers. 31
As the number of streaming multiprocessors (SMs) in GPUs increases, in order to gain better performance, the reply network faces heavy traffic. This causes congestion on Network-on-Chip (NoC) routers and memory controller’s (MC) buffers. By taking
Externí odkaz:
https://explore.openaire.eu/search/publication?articleId=doi_________::57ef7913795f2fdf3f927ef72db725dd
https://doi.org/10.1142/s0218126622500153
https://doi.org/10.1142/s0218126622500153
Publikováno v:
IEEE Transactions on Very Large Scale Integration (VLSI) Systems. 27:2331-2343
Integrity trees are widely used in computer systems to prevent replay, splicing, and spoofing attacks on memories. Such mechanisms incur excessive performance and energy overhead. We propose a memory authentication framework that combines architectur
Externí odkaz:
https://explore.openaire.eu/search/publication?articleId=doi_________::4918bfba278529b8bc1767f0f6bb3696
https://doi.org/10.1109/tvlsi.2019.2923004
https://doi.org/10.1109/tvlsi.2019.2923004
Publikováno v:
Journal of Systems Architecture. 98:424-433
The Network-on-Chip(NoC) is a promising alternative to traditional bus-based architectures that has been widely applied to interconnect multi/many-core systems due to its scalable and modular design. Undoubtedly, the memory wall problem is one of the
Externí odkaz:
https://explore.openaire.eu/search/publication?articleId=doi_dedup___::dfeeb277ad8e06ab84178adee57eef73
https://doi.org/10.1016/j.sysarc.2019.05.002
https://doi.org/10.1016/j.sysarc.2019.05.002