Zobrazeno 1 - 10
of 1 184
pro vyhledávání: '"fd-soi"'
Publikováno v:
IEEE Access, Vol 12, Pp 147809-147827 (2024)
This paper proposes a design-oriented DC model for MOS transistors in advanced nanometric technologies, based on only six parameters. The proposed model is based on the inversion charge and includes the main short-channel effects for accurately descr
Externí odkaz:
https://doaj.org/article/962cef9c06f44342b457b0999df4ffe2
Publikováno v:
IEEE Access, Vol 12, Pp 111627-111637 (2024)
This paper investigates a 60 GHz low-power broadband low noise amplifier (LNA) with variable gain control. To prove the concept, the circuit is implemented in a 22nm fully depleted silicon on insulator (FD-SOI) CMOS technology. It supports broadband
Externí odkaz:
https://doaj.org/article/dadcfdcb23b9428fb25cab2a0beb6bfe
Autor:
Deni Germano Alves Neto, Mohamed Khalil Bouchoucha, Gabriel Maranhao, Manuel J. Barragan, Marcio Cherem Schneider, Andreia Cathelin, Sylvain Bourdel, Carlos Galup-Montoro
Publikováno v:
IEEE Access, Vol 12, Pp 87420-87437 (2024)
This paper presents a novel charge-based MOSFET model, denoted ACM2, including velocity saturation and drain-induced barrier lowering. Employing the proposed model, all the DC characteristics (currents and charges) and the small-signal equations can
Externí odkaz:
https://doaj.org/article/42df70ed6c7345dda9dc8fb338bbfaa6
Publikováno v:
IEEE Access, Vol 12, Pp 87065-87076 (2024)
In this paper, a quad-core oscillator is presented, which exploits a novel stacked two-port inductor topology to couple four oscillator cores. The topology guarantees excellent low-phase-noise performance, while overcoming the drawbacks of multi-core
Externí odkaz:
https://doaj.org/article/4136f8377d4249758f78ab7fb187bba7
Autor:
Shaochen Gao, Duc-Tung Vu, Thibauld Cazimajou, Patrick Pittet, Martine Le Berre, Mohammadreza Dolatpoor Lakeh, Fabien Mandorlo, Régis Orobtchouk, Jean-Baptiste Schell, Jean-Baptiste Kammerer, Andreia Cathelin, Dominique Golanski, Wilfried Uhring, Francis Calmon
Publikováno v:
Photonics, Vol 11, Iss 6, p 526 (2024)
The integration of Single-Photon Avalanche Diodes (SPADs) in CMOS Fully Depleted Silicon-On-Insulator (FD-SOI) technology under a buried oxide (BOX) layer and a silicon film containing transistors makes it possible to realize a 3D SPAD at the chip le
Externí odkaz:
https://doaj.org/article/ac80468040404a60aef0d5871a92f1c9
Publikováno v:
Applied Sciences, Vol 14, Iss 7, p 3080 (2024)
This paper presents a broadband millimeter-wave (mm-Wave) low noise amplifier (LNA) designed in a 22 nm fully depleted silicon-on-insulator (FD-SOI) CMOS technology. Electromagnetic (EM) simulations suggest that the LNA has a 3-dB bandwidth (BW) from
Externí odkaz:
https://doaj.org/article/14e3d99344cc40479a7c0f18a1faa146
Publikováno v:
IEEE Journal of the Electron Devices Society, Vol 11, Pp 650-657 (2023)
Advances in CMOS technology have enabled MOSFET with cutoff and maximum oscillation frequencies (ft and fmax) in the 400 GHz range, thus opening the path to CMOS-based applications at millimeter-wave (mm-wave) and sub-THz frequencies. Accurate compac
Externí odkaz:
https://doaj.org/article/617cd55939e5468097b07496546d68a5
Publikováno v:
IEEE Journal on Exploratory Solid-State Computational Devices and Circuits, Vol 9, Iss 2, Pp 159-167 (2023)
This article presents the flipped (F)-2T2R resistive random access memory (RRAM) compute cell enhancing the performance of RRAM-based mixed-signal accelerators for deep neural networks (DNNs) in machine-learning (ML) applications. The F-2T2R cell is
Externí odkaz:
https://doaj.org/article/9e67aea22ed44814bf0a3db8e7495b83
Publikováno v:
IEEE Journal of the Electron Devices Society, Vol 11, Pp 22-29 (2023)
In this paper, we present on the cryogenic characterization of short channel 28-nm FD-SOI nMOS and pMOS transistors having widths of the $1 ~\mu \text{m}$ and $0.08 ~\mu \text{m}$ at temperatures ranging from T = 300 K down to T = 10 K. We report, fo
Externí odkaz:
https://doaj.org/article/e35360b0937e4a388874b41841b4ce5a
Publikováno v:
IEEE Open Journal of the Solid-State Circuits Society, Vol 2, Pp 135-143 (2022)
In this article, a 3-GS/s time-interleaved (TI) RF track-and-hold (TaH) amplifier designed in a 22-nm SOI technology is presented. The TaH amplifier is designed to drive an ADC, which can be either two pipeline-ADCs or two rows of SAR-ADCs. Both TI T
Externí odkaz:
https://doaj.org/article/95ff94c6aac74b3f84f06faff8d46d37