Zobrazeno 1 - 10
of 36
pro vyhledávání: '"dynamically reconfigurable resource array (DRRA)"'
Autor:
Dhilleswararao Pudi, Yu Yang, Dimitrios Stathis, Sunil Kumar Prajapati, Srinivas Boppu, Ahmed Hemani, Linga Reddy Cenkeramaddi
Publikováno v:
IEEE Access, Vol 12, Pp 155885-155903 (2024)
Efficiently synthesizing an entire application that consists of multiple algorithms for hardware implementation is a very difficult and unsolved problem. One of the main challenges is the lack of good algorithmic libraries. A good algorithmic library
Externí odkaz:
https://doaj.org/article/d5da1297f8574bae87ac797fa1f57b5c
Akademický článek
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Publikováno v:
Design Automation for Embedded Systems; Jun2024, Vol. 28 Issue 2, p155-186, 32p
Autor:
Dhilleswararao Pudi, Shivam Malviya, Srinivas Boppu, Yu Yang, Ahmed Hemani, Linga Reddy Cenkeramaddi
Publikováno v:
IEEE Access, Vol 12, Pp 124081-124094 (2024)
Coarse-Grained Reconfigurable Array (CGRA) architectures are potential high-performance and power-efficient platforms. However, mapping applications efficiently on CGRA, which includes scheduling and binding operations on functional units and variabl
Externí odkaz:
https://doaj.org/article/90e050bb4b894cbb8272c59e66c4744d
Autor:
Xu, Zihao
With the increasing complexity of the chip architecture design for meeting different application requirements, the corresponding instruction scheduler of high-level synthesis tool needs to solve complex scheduling problems. Dynamically Reconfigurable
Externí odkaz:
http://urn.kb.se/resolve?urn=urn:nbn:se:kth:diva-332071
Publikováno v:
Journal of Signal Processing Systems for Signal, Image & Video Technology; May2019, Vol. 91 Issue 5, p459-473, 15p
Autor:
Wang, Yuxuan
Vesyla-II is developed as the High-Level Synthesis (HLS) tool serving the SiLago platform. The assembler Manas is a part of the Coarse Grain Reconfigurable Architectures (CGRA) compiler in Vesyla-II, which is used to transform the information from so
Externí odkaz:
http://urn.kb.se/resolve?urn=urn:nbn:se:kth:diva-324008
Autor:
Wang, Yuxuan
Vesyla-II is developed as the High-Level Synthesis (HLS) tool serving the SiLago platform. The assembler Manas is a part of the Coarse Grain Reconfigurable Architectures (CGRA) compiler in Vesyla-II, which is used to transform the information from so
Externí odkaz:
https://explore.openaire.eu/search/publication?articleId=od_______260::2bac4307986808709c51d79ed5c4b288
http://urn.kb.se/resolve?urn=urn:nbn:se:kth:diva-324008
http://urn.kb.se/resolve?urn=urn:nbn:se:kth:diva-324008
Autor:
Tajammul, Muhammad Adeel, Jafri, S.M.A., Ellerve, Peeter, Hemani, Ahmed, Tenhunen, Hannu, Plosila, Juha
Publikováno v:
2015 28th International Conference on VLSI Design; 2015, p547-552, 6p
Autor:
Ngyen, Tuan, Jafri, Syed M.A.H., Daneshtalab, Masoud, Hemani, Ahmed, Dytckov, Sergei, Plosila, Juha, Tenhunen, Hannu
Publikováno v:
2015 23rd Euromicro International Conference on Parallel, Distributed & Network-Based Processing; 2015, p751-758, 8p