Zobrazeno 1 - 10 of 95 pro vyhledávání: '"comparator offset"'
1
Akademický článek
A Design of 44.1 fJ/Conv-Step 12-Bit 80 ms/s Time Interleaved Hybrid Type SAR ADC With Redundancy Capacitor and On-Chip Time-Skew Calibration
Autor: Deeksha Verma, Behnam S. Rikan, Khuram Shehzad, Sung Jin Kim, Danial Khan, Venkatesh Kommangunta, Syed Adil Ali Shah, Younggun Pu, Sang-Sun Yoo, Keum Cheol Hwang, Youngoo Yang, Kang-Yoon Lee
Publikováno v: IEEE Access, Vol 9, Pp 133143-133155 (2021)
A 12-bit 80 MS/s hybrid type analog-to-digital converter (ADC) for high sampling speed and low power applications is presented in this paper. It has a subranging architecture with a front end of 6-bit Flash ADC with five channels of 6-bit time interl
Externí odkaz: https://doaj.org/article/228a3f0ef92741c285ae1b583f1419cb
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2
Akademický článek
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3
Akademický článek
Analysis of Residue Probability Density Function and Comparator Offset Error in Pipelined ADCs
Autor: E. Fatemi-Behbahani, E. Farshidi, K. Ansari-Asl
Publikováno v: Radioengineering, Vol 25, Iss 1, Pp 208-215 (2016)
This paper presents a new approach to analyze the convergence of residue probability density function (pdf) in pipelined ADCs. Compared to the previous approaches, in the proposed approach, in addition to the analysis of residue pdfs for different in
Externí odkaz: https://doaj.org/article/56573939da55467db5cc00cb7f7dff69
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4
Akademický článek
Time-Interleaved SAR ADC with Background Timing-Skew Calibration for UWB Wireless Communication in IoT Systems
Autor: Kiho Seong, Dong-Kyu Jung, Dong-Hyun Yoon, Jae-Soub Han, Ju-Eon Kim, Tony Tae-Hyoung Kim, Woojoo Lee, Kwang-Hyun Baek
Publikováno v: Sensors, Vol 20, Iss 8, p 2430 (2020)
Ultra-wideband (UWB) wireless communication is prospering as a powerful partner of the Internet-of-things (IoT). Due to the ongoing development of UWB wireless communications, the demand for high-speed and medium resolution analog-to-digital converte
Externí odkaz: https://doaj.org/article/3879131b6b0c4ed9873858142b1a3441
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5
Akademický článek
A 12-bit 30 MS/s Successive Approximation-Register Analog-to-Digital Converter with Foreground Digital Calibration Algorithm
Autor: Shouping Li, Yang Guo, Jianjun Chen, Bin Liang
Publikováno v: Symmetry, Vol 12, Iss 1, p 165 (2020)
This paper presents a foreground digital calibration algorithm based on a dynamic comparator that aims to reduce comparator offset and capacitor mismatch, as well as improve the performance of the successive approximation analog-to-digital converter
Externí odkaz: https://doaj.org/article/c59e1fd7df664065a8dde1708c153362
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6
A Design of 44.1 fJ/Conv-Step 12-Bit 80 ms/s Time Interleaved Hybrid Type SAR ADC With Redundancy Capacitor and On-Chip Time-Skew Calibration
Autor: Khuram Shehzad, Youngoo Yang, Sang-Sun Yoo, Syed Adil Ali Shah, Keum Cheol Hwang, Kang-Yoon Lee, Behnam Samadpoor Rikan, Danial Khan, Deeksha Verma, SungJin Kim, YoungGun Pu, Venkatesh Kommangunta
Publikováno v: IEEE Access, Vol 9, Pp 133143-133155 (2021)
A 12-bit 80 MS/s hybrid type analog-to-digital converter (ADC) for high sampling speed and low power applications is presented in this paper. It has a subranging architecture with a front end of 6-bit Flash ADC with five channels of 6-bit time interl
Externí odkaz: https://explore.openaire.eu/search/publication?articleId=doi_dedup___::5bfc2eb09e1d7c56b5f84fa5205ec4d4
https://ieeexplore.ieee.org/document/9548087/
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7
Akademický článek
A 1.15 μW 200 kS/s 10-b Monotonic SAR ADC Using Dual On-Chip Calibrations and Accuracy Enhancement Techniques
Autor: Jae-Hun Lee, Dasom Park, Woojin Cho, Huu Nhan Phan, Cong Luong Nguyen, Jong-Wook Lee
Publikováno v: Sensors, Vol 18, Iss 10, p 3486 (2018)
Herein, we present an energy efficient successive-approximation-register (SAR) analog-to-digital converter (ADC) featuring on-chip dual calibration and various accuracy-enhancement techniques. The dual calibration technique is realized in an energy a
Externí odkaz: https://doaj.org/article/636488ee08f7415eb9e26e48291cb496
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8
A 6GS/s 0.5GHz BW continuous-time 2-1-1 MASH ΔΣ modulator with phase-boosted current-mode ELD compensation in 40nm CMOS
Autor: Georgi Radulov, Robert Rutten, Q. Liu, Muhammed Bolatkale, C. Zhang, Lucien J. Breems, S. Bajoria, A.H.M. van Roermund
Publikováno v: ESSCIRC 2021-IEEE 47th European Solid State Circuits Conference (ESSCIRC), 491-494
STARTPAGE=491;ENDPAGE=494;TITLE=ESSCIRC 2021-IEEE 47th European Solid State Circuits Conference (ESSCIRC)
ESSCIRC
This paper presents a 6GS/s 0.5GHz bandwidth CT 2-1-1 MASH 3b ΔΣ modulator in 40nm CMOS. To enable the 0.5GHz bandwidth, the modulator employs current-mode excess loop delay compensation with phase boosting, current-mode locally-time-interleaved qu
Externí odkaz: https://explore.openaire.eu/search/publication?articleId=doi_dedup___::bfb5076c6531788c9a53ac4f5dd8c029
https://research.tue.nl/nl/publications/1bccb076-3194-4288-83c2-8648f8c1cc06
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9
Akademický článek
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10
A 12-bit 30 MS/s Successive Approximation-Register Analog-to-Digital Converter with Foreground Digital Calibration Algorithm
Autor: Jianjun Chen, Bin Liang, Yang Guo, Shouping Li
Publikováno v: Symmetry
Volume 12
Issue 1
Symmetry, Vol 12, Iss 1, p 165 (2020)
This paper presents a foreground digital calibration algorithm based on a dynamic comparator that aims to reduce comparator offset and capacitor mismatch, as well as improve the performance of the successive approximation analog-to-digital converter
Externí odkaz: https://explore.openaire.eu/search/publication?articleId=doi_dedup___::99e6f6d37e4a7171ec29bbcda8fb41b6
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