Zobrazeno 1 - 10
of 185
pro vyhledávání: '"clock distribution networks"'
Autor:
Greengard, Samuel
Publikováno v:
Communications of the ACM; Sep2024, Vol. 67 Issue 9, p16-18, 3p
Autor:
Nagarathna R., Aswat, A. R.
Publikováno v:
Proceedings on Engineering Sciences; 2024, Vol. 6 Issue 3, p903-914, 12p
Autor:
Ewetz, Rickard1, Koh, Cheng-Kok2
Publikováno v:
IEEE Transactions on Computer-Aided Design of Integrated Circuits & Systems. Jun2019, Vol. 38 Issue 6, p1161-1174. 14p.
Autor:
Kansal, Shubhi1 kansalshubhi@yahoo.com
Publikováno v:
IUP Journal of Electrical & Electronics Engineering. Oct2013, Vol. 6 Issue 4, p7-12. 6p.
Publikováno v:
Electronics Letters (Wiley-Blackwell). 3/7/2019, Vol. 55 Issue 5, p244-246. 3p.
Publikováno v:
Electronics Letters, Vol 59, Iss 8, Pp n/a-n/a (2023)
Abstract This paper proposes a small‐area and low‐power all‐digital duty cycle corrector with de‐skew circuit. By adopting the proposed delay unit containing a pre‐charge transistor, half cycle delay line can accurately generate half‐cycl
Externí odkaz:
https://doaj.org/article/84ff5ff2ed6644bf8f0b59c7d2cd1428
Autor:
Islam, Riadul, Guthaus, Matthew R.
Publikováno v:
IEEE Transactions on Circuits & Systems. Part I: Regular Papers. Jan2019, Vol. 66 Issue 1, p251-262. 12p.
Publikováno v:
IEEE Transactions on Components, Packaging & Manufacturing Technology. Nov2015, Vol. 5 Issue 11, p1669-1678. 10p.
Publikováno v:
IEEE Transactions on Computer-Aided Design of Integrated Circuits & Systems. Dec2015, Vol. 34 Issue 12, p1954-1963. 10p.
Publikováno v:
IEEE Transactions on Computer-Aided Design of Integrated Circuits & Systems. Apr2015, Vol. 34 Issue 4, p589-602. 14p.