Zobrazeno 1 - 10
of 46
pro vyhledávání: '"Zurab Khasidashvili"'
Autor:
Zurab Khasidashvili, Adam J. Norman
Publikováno v:
International Journal of Data Science and Analytics. 11:195-219
We propose a feature range analysis algorithm whose aim is to derive features that explain the response variable better than the original features. Moreover, for binary classification problems, and for regression problems where positive and negative
Externí odkaz:
https://explore.openaire.eu/search/publication?articleId=doi_________::48f3987773a31f8feb014db9ab9f0022
https://doi.org/10.1007/s41060-021-00251-7
https://doi.org/10.1007/s41060-021-00251-7
Publikováno v:
Proceedings of the Thirty-First International Joint Conference on Artificial Intelligence.
Application domains of Bayesian optimization include optimizing black-box functions or very complex functions. The functions we are interested in describe complex real-world systems applied in industrial settings. Even though they do have explicit re
Externí odkaz:
https://explore.openaire.eu/search/publication?articleId=doi_________::e251ae54950d308e438f13d121657eab
https://doi.org/10.24963/ijcai.2022/249
https://doi.org/10.24963/ijcai.2022/249
Publikováno v:
2021 IEEE 71st Electronic Components and Technology Conference (ECTC).
This paper describes a systematic approach for system design space exploration through the application of machine learning (ML) methods for advanced system analysis. A demonstration of applying this method for signal integrity analysis, and a case st
Externí odkaz:
https://explore.openaire.eu/search/publication?articleId=doi_________::ffb692810c89ab6de0aa60ca9f7d8c5d
https://doi.org/10.1109/ectc32696.2021.00201
https://doi.org/10.1109/ectc32696.2021.00201
Autor:
Tanmay Haldankar, Dinesh Chhatani, Zurab Khasidashvili, Rakesh Mistry, Carl-Johan H. Seger, Rajkumar Gajavelly, Supratik Chakraborty
Publikováno v:
Formal Methods in System Design. 50:317-352
Symbolic trajectory evaluation (STE) is a model checking technique that has been successfully used to verify many industrial designs. Existing implementations of STE reason at the level of bits, allowing signals in a circuit to take values from a lat
Externí odkaz:
https://explore.openaire.eu/search/publication?articleId=doi_dedup___::c7bf08bf618cefb0eb5081af648f462c
https://doi.org/10.1007/s10703-017-0268-9
https://doi.org/10.1007/s10703-017-0268-9
Autor:
Zurab Khasidashvili, Adam J. Norman
Publikováno v:
DSAA
We propose a supervised learning algorithm whose aim is to derive features that explain the response variable better than the original features. Moreover, when there is a meaning for positive vs negative samples, our aim is to derive features that ex
Externí odkaz:
https://explore.openaire.eu/search/publication?articleId=doi_________::d8c1136a09da75c3d14972c1688fb2ab
https://doi.org/10.1109/dsaa.2019.00045
https://doi.org/10.1109/dsaa.2019.00045
Publikováno v:
GCAI
In recent years it was proposed to encode bounded model checking (BMC) into the effectively propositional fragment of first-order logic (EPR). The EPR fragment can provide for a succinct representation of the problem and facilitate reasoning at a hig
Externí odkaz:
https://explore.openaire.eu/search/publication?articleId=doi_________::da33f2ca134a100610569c7dd97898ca
https://doi.org/10.29007/scv7
https://doi.org/10.29007/scv7
Publikováno v:
Theory and Applications of Satisfiability Testing – SAT 2016 ISBN: 9783319409696
SAT
SAT
Preprocessing plays a major role in efficient propositional reasoning but has been less studied in first-order theorem proving. In this paper we propose a predicate elimination procedure which can be used as a preprocessing step in first-order theore
Externí odkaz:
https://explore.openaire.eu/search/publication?articleId=doi_________::68c32fe3167876bf3347c0d3c5be9cde
https://doi.org/10.1007/978-3-319-40970-2_22
https://doi.org/10.1007/978-3-319-40970-2_22
Autor:
Roberto Sebastiani, Zurab Khasidashvili, Amit Palti, Roberto Bruttomesso, Marco Bozzano, Alessandro Cimatti, Anders Franzén, Ziyad Hanna
Publikováno v:
Electronic Notes in Theoretical Computer Science. 144(2):3-14
Formal checking at Register-Transfer Level (RTL) is currently a fundamental step in the design of hardware circuits. Most tools for formal checking, however, work at the boolean level, which is not expressive enough to capture the abstract, high leve
Externí odkaz:
https://explore.openaire.eu/search/publication?articleId=doi_dedup___::5c5d67e65236ec3df31c67e9e0c96e34
Autor:
John Glauert, Zurab Khasidashvili
Publikováno v:
Electronic Notes in Theoretical Computer Science. 86(4):689-713
In previous works, we introduced Stable Deterministic Residual Structures (SDRSs), Abstract Reduction Systems with an axiomatized residual relation which model orthogonal term and graph rewriting systems, and Deterministic Family Structures (DFSs), w
Externí odkaz:
https://explore.openaire.eu/search/publication?articleId=doi_dedup___::edeee26aba4272265eebaf68a21f9857
Autor:
Ziyad Hanna, Zurab Khasidashvili
Publikováno v:
Electronic Notes in Theoretical Computer Science. 89:593-607
The BDD- and SAT-based model checking and verification methods normally require an initial state. Here we are concerned with sequential hardware verification, where an initial state must be one of the reset states. In practice, a reset state is not a
Externí odkaz:
https://explore.openaire.eu/search/publication?articleId=doi_dedup___::be792525eeac94cfc5499b6af58cd60f
https://doi.org/10.1016/s1571-0661(05)82545-9
https://doi.org/10.1016/s1571-0661(05)82545-9