Zobrazeno 1 - 2
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pro vyhledávání: '"Zi-qiao Chu"'
Publikováno v:
2008 9th International Conference on Solid-State and Integrated-Circuit Technology.
This paper describes a phase-locked loop (PLL) designed for clock multiplication. The PLL has a locking range from 10 MHz to 600 MHz at 1.8 V power supply. It has a very low peak-to-peak jitter which less than 50 ps at 150 MHz output frequency. It ha
Externí odkaz:
https://explore.openaire.eu/search/publication?articleId=doi_________::7314a92101869886cfa2ab25a6c9613d
https://doi.org/10.1109/icsict.2008.4734970
https://doi.org/10.1109/icsict.2008.4734970
Publikováno v:
2008 9th International Conference on Solid-State & Integrated-Circuit Technology; 2008, p1929-1932, 4p