Zobrazeno 1 - 4
of 4
pro vyhledávání: '"Zi-Hong Jiang"'
Autor:
Ming-Dou Ker, Zi-Hong Jiang
Publikováno v:
IEEE Journal of the Electron Devices Society, Vol 11, Pp 141-152 (2023)
In CMOS chips, the wider layout rules were traditionally applied to overcome latch-up issues. However, the chip area with wider layout rules was often enlarged, and in turn the chip cost was also increased. To effectively improve latch-up immunity wi
Externí odkaz:
https://doaj.org/article/35a58b0a15524d7ba1c46ddc5c8cd900
Autor:
Zi-Hong Jiang, Ming-Dou Ker
Publikováno v:
IEEE Journal of the Electron Devices Society, Vol 10, Pp 516-524 (2022)
As the high-voltage (HV) and low-voltage (LV) circuits are integrated together in a common silicon substrate, the parasitic latch-up path between neighboring HV and LV circuits with limited spacing in layout would be triggered into latch-up state to
Externí odkaz:
https://doaj.org/article/611b108235154981871b5f39b9f69913
Autor:
Zi-Hong Jiang, Ming-Dou Ker
Publikováno v:
IEEE Transactions on Electromagnetic Compatibility. 64:1785-1792
Externí odkaz:
https://explore.openaire.eu/search/publication?articleId=doi_________::8775e205f85a51622b7952b5d2015f56
https://doi.org/10.1109/temc.2022.3202806
https://doi.org/10.1109/temc.2022.3202806
Autor:
Zi-Hong Jiang, Ming-Dou Ker
Publikováno v:
IEEE Electron Device Letters. 43:604-606
Externí odkaz:
https://explore.openaire.eu/search/publication?articleId=doi_________::1ebc28fd871490a39bed69b1b90c238a
https://doi.org/10.1109/led.2022.3155480
https://doi.org/10.1109/led.2022.3155480