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pro vyhledávání: '"Zhi-Heng Kang"'
Autor:
Zhi-Heng Kang, Shen-Iuan Liu
Publikováno v:
IEEE Journal of Solid-State Circuits. 58:806-816
Publikováno v:
2022 International Symposium on VLSI Design, Automation and Test (VLSI-DAT).
Publikováno v:
VLSI-DAT
A digital phase-locked loop (DPLL) using the proposed adaptive loop gain controller (ALGC) is presented. The ALGC uses a spectrum-balancing technique to detect the difference of the high-frequency and the low-frequency powers of the bang-bang phase-f