Zobrazeno 1 - 10
of 39
pro vyhledávání: '"Zhi-Cheng Hsiao"'
Autor:
Zhi-Cheng Hsiao, 蕭志誠
90
This thesis discusses the fabrication of the microaccelerometer using piezoelectric thin film. The manufacturing processes under investigation include the film deposition, the surface micromachining, and the bulk micromachining. The manufactu
This thesis discusses the fabrication of the microaccelerometer using piezoelectric thin film. The manufacturing processes under investigation include the film deposition, the surface micromachining, and the bulk micromachining. The manufactu
Externí odkaz:
http://ndltd.ncl.edu.tw/handle/74625690570595592372
Autor:
Kuan-Neng Chen, Wei-Chung Lo, Dian-Rong Lyu, Zhi-Cheng Hsiao, Huan-Chun Fu, Hsiang-Hung Chang, Cheng-Ta Ko, C. H. Chien, Chao-Kai Hsu
Publikováno v:
IEEE Transactions on Device and Materials Reliability. 14:715-720
A novel backside-illuminated CMOS image sensor (BSI-CIS) scheme and process are developed and demonstrated. This innovative scheme can be realized without fusion oxide bonding and through-silicon via (TSV) fabrication. This wafer-level TSV-less BSI-C
Externí odkaz:
https://explore.openaire.eu/search/publication?articleId=doi_________::d29d6041c8667c0c9702d4d53158c3f0
https://doi.org/10.1109/tdmr.2014.2311887
https://doi.org/10.1109/tdmr.2014.2311887
Autor:
Yu-Lan Lu, Jui-Hsiung Huang, Ming-Jer Kao, Cheng-Ta Ko, Huan-Chun Fu, Ching-Kuan Lee, Robert Lo, Ren-Shin Cheng, Zhi-Cheng Hsiao, Kuo-Shu Kao, John H. Lau, Pei-Chen Chang, Yu-Jiau Huang, Tao-Chih Chang
Publikováno v:
IEEE Transactions on Components, Packaging and Manufacturing Technology. 2:1229-1238
In this investigation, Cu-Sn lead-free solder microbumps on 10-μm pads with a 20-μm pitch are designed and fabricated. The chip size is 5 × 5 mm with thousands of microbumps. A daisy-chain feature is adopted for the characterization and reliabilit
Externí odkaz:
https://explore.openaire.eu/search/publication?articleId=doi_________::e2ecd2b50efcb192420ae9abf594659b
https://doi.org/10.1109/tcpmt.2012.2189397
https://doi.org/10.1109/tcpmt.2012.2189397
Autor:
Cheng-Ta Ko, Kuan-Neng Chen, Peng-Shu Chen, Yu-Hua Chen, Shyh-Shyuan Sheu, Jui-Hsiung Huang, Yu-Jiau Hwang, Zhi-Cheng Hsiao, Huan-Chun Fu, Yao-Jen Chang, Chia-Wen Chiang, Wei-Chung Lo
Publikováno v:
IEEE Transactions on Device and Materials Reliability. 12:209-216
Thin wafer/chip stacking with vertical interconnect by a Cu through-silicon via (TSV) and a Cu/Sn microjoint is one of the candidates for 3-D integration. The insertion loss of the two-chip stack was evaluated with different TSV pitches, microbump di
Externí odkaz:
https://explore.openaire.eu/search/publication?articleId=doi_________::d78b123e000ab7e25fe335f85b6fd39b
https://doi.org/10.1109/tdmr.2012.2195005
https://doi.org/10.1109/tdmr.2012.2195005
Publikováno v:
Journal of Nanoscience and Nanotechnology. 12:1821-1828
Hybrid bonding, an emerging bonding approach with high yield and reliability, can achieve vertical interconnection with adhesive serving reinforcement of the mechanical stability between stacked ICs. To develop metal/adhesive hybrid bonding technolog
Externí odkaz:
https://explore.openaire.eu/search/publication?articleId=doi_dedup___::e9564c2f94781975dabcecfe0d343805
https://doi.org/10.1166/jnn.2012.5176
https://doi.org/10.1166/jnn.2012.5176
Autor:
Zhi-Cheng Hsiao, Wei-Chung Lo, Huan-Chun Fu, Wen-Wei Shen, Chia-Wei Chiang, Chao-Kai Hsu, Hsiang-Hung Chang, Cheng-Ta Ko
Publikováno v:
2015 International Conference on Electronic Packaging and iMAPS All Asia Conference (ICEP-IAAC).
In this research, the wafer level Cu/BCB hybrid bonding with TSV for 3D integration by using fly cutting technology is proposed. As we know Cu bump surface is rough by electroplating, and BCB is spin-coated on Cu bump wafer induced high topography. C
Externí odkaz:
https://explore.openaire.eu/search/publication?articleId=doi_________::1a132640195816ff159bf02fa36ee6b3
https://doi.org/10.1109/icep-iaac.2015.7111128
https://doi.org/10.1109/icep-iaac.2015.7111128
Autor:
Ding-Ming Kwai, Jen-Chun Wang, Hsiang-Hung Chang, Chung-Chih Wang, Cheng-Ta Ko, Pei-Jer Tzeng, Chau-Jie Zhan, Chia-Hsin Lee, Zhi-Cheng Hsiao, Yu-Chen Hsin, Yung-Fa Chou, Chun-Hsien Chien, Yu-Wei Huang, Ting-Sheng Chen, Wei-Chung Lo, Cha-Hsin Lin, Tzu-Kun Ku, Ming-Jer Kao
Publikováno v:
2015 International Symposium on VLSI Technology, Systems and Applications.
A novel low cost backside illuminated CMOS image sensor structure is proposed in this research. By using thin wafer handling technology, the wafer is thinned down to less than 5 μm and no TSV and direct bonding process are needed in this low cost so
Externí odkaz:
https://explore.openaire.eu/search/publication?articleId=doi_________::d1301a135cc2aa8f4f91ccbbb2b95b32
https://doi.org/10.1109/vlsi-tsa.2015.7117587
https://doi.org/10.1109/vlsi-tsa.2015.7117587
Autor:
Ting-Sheng Chen, Chau-Jie Zhan, Yu-Chen Hsin, Cheng-Ta Ko, Ming-Jer Kao, Wei-Chung Lo, C. H. Chien, Pei-Jer Tzeng, Zhi-Cheng Hsiao, Hsiang-Hung Chang
Publikováno v:
Proceedings of the 5th Electronics System-integration Technology Conference (ESTC).
In this research, a new structure and process integration for backside illuminated CMOS image sensor by using thin wafer handling technology is proposed. First of all, the wafer of a 3 Mega pixel CMOS image sensor is temporary bonded to a silicon car
Externí odkaz:
https://explore.openaire.eu/search/publication?articleId=doi_________::38f7ecee8c0a06bbc3773babee332edb
https://doi.org/10.1109/estc.2014.6962709
https://doi.org/10.1109/estc.2014.6962709
Autor:
John H. Lau, Chau-Jie Zhan, Chun-Hsien Chien, Ming-Ji Dai, Ra-Min Tain, Ming-Jer Kao, Yu-Mei Cheng, Pai-Cheng Chang, W. L. Tsai, Sheng-Tsai Wu, Yu-Lin Chao, Ren-Shin Cheng, Heng-Chieh Chien, Li-Ling Liao, Zhi-Cheng Hsiao, Yuan-Chang Lee, Ching-Kuan Lee, Yu-Wei Huang, Wei-Chung Lo, Huan-Chun Fu
Publikováno v:
2014 IEEE 64th Electronic Components and Technology Conference (ECTC).
In this investigation, a SiP (system-in-package) which consists of a very low-cost interposer with through-silicon holes (TSHs) and with chips on its top- and bottom-side (a real 3D IC integration) is studied. Emphasis is placed on the fabrication of
Externí odkaz:
https://explore.openaire.eu/search/publication?articleId=doi_________::db29d6450e946c0c6833ece0a43ee5f9
https://doi.org/10.1109/ectc.2014.6897301
https://doi.org/10.1109/ectc.2014.6897301
Autor:
Jen-Chun Wang, Pei-Jer Tzeng, Cheng-Ta Ko, Chau-Jie Zhan, Ting-Sheng Chen, S. M. Lee, C. H. Lee, Ming-Jer Kao, C. H. Chien, Yu-Wei Huang, Wei-Chung Lo, Hsiang-Hung Chang, Yuan-Chang Lee, Zhi-Cheng Hsiao
Publikováno v:
2014 International Conference on Electronics Packaging (ICEP).
In this research, a new structure and process integration for backside illuminated CMOS image sensor by using thin wafer handling technology is proposed. First of all, the wafer of a 3 Mega pixel CMOS image sensor is temporary bonded to a silicon car
Externí odkaz:
https://explore.openaire.eu/search/publication?articleId=doi_________::321f28c7e98b54cf078ea635b95cddd4
https://doi.org/10.1109/icep.2014.6826657
https://doi.org/10.1109/icep.2014.6826657