Zobrazeno 1 - 5
of 5
pro vyhledávání: '"Zhe Lei Xia"'
Publikováno v:
2009 17th IFIP International Conference on Very Large Scale Integration (VLSI-SoC).
This paper proposes an efficient multiresolution motion estimation algorithm (MMEA) well-suited for high definition video encoder VLSI implementation. 16-way parallel process element arrays achieve fast search with regular data access and efficient d
Externí odkaz:
https://explore.openaire.eu/search/publication?articleId=doi_________::e4411cc9267f8ac125e7aa569227581d
https://doi.org/10.1109/vlsisoc.2009.6041353
https://doi.org/10.1109/vlsisoc.2009.6041353
Publikováno v:
ISCAS
A dedicated VLSI architecture is proposed to implement rate distortion optimization (RDO) for AVS video coding, with 4CIF format video supported at a system clock of 54 MHZ for low power applications. The seven-step block level pipeline architecture
Externí odkaz:
https://explore.openaire.eu/search/publication?articleId=doi_________::72618e10e7c6ce00f2ee5654397d9d00
https://doi.org/10.1109/iscas.2008.4542040
https://doi.org/10.1109/iscas.2008.4542040
Publikováno v:
Advances in Multimedia Information Processing – PCM 2007 ISBN: 9783540772545
PCM
PCM
This paper proposes a cost-effective VLSI architecture to improve the three-step search (TSS) algorithm for efficient motion estimation. A weighted SAD is defined as the new distortion measure instead of SAD for motion vector selection to remedy the
Externí odkaz:
https://explore.openaire.eu/search/publication?articleId=doi_________::b518327efcb4b8b71476b0b012ef46ed
https://doi.org/10.1007/978-3-540-77255-2_98
https://doi.org/10.1007/978-3-540-77255-2_98
Publikováno v:
2009 17th IFIP International Conference on Very Large Scale Integration (VLSI-SoC); 2009, p189-192, 4p
Publikováno v:
2008 IEEE International Symposium on Circuits & Systems; 2008, p2805-2808, 4p