Zobrazeno 1 - 1
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pro vyhledávání: '"Zhai Feixue"'
Publikováno v:
Dianzi Jishu Yingyong, Vol 45, Iss 8, Pp 48-52 (2019)
For high-performance chip designs with ever-increasing scale and increasing operating frequency, performance has always been the focus and difficulty of physical design. The buffer is inserted to minimize signal line delay, which optimizes timing and
Externí odkaz:
https://doaj.org/article/999026a0b9d84d1c82983423edbc1189
