Design for test and reliability in ultimate CMOS

Autor: Nicolaidis, M., Anghel, L., Zergainoh, N., Zorian, Y., Karnik, T., Bowman, K., Tschanz, J., Lu, S.-L., Tokunaga, C., Raychowdhury, A., Khellah, M., Kulkarini, J., Vivek, De, Avresky, D.

Publikováno v: Proc. of Design, Automation and Test in Europe (DATE'12)
Design, Automation and Test in Europe (DATE'12)
Design, Automation and Test in Europe (DATE'12), Mar 2012, Dresden, Germany. pp.677-682

ISBN 978-3-9810801-8-6; International audience; This session brings together specialists from the DfT, DfY and DfR domains that will address key problems together with their solutions for the 14nm node and beyond, dealing with extremely complex chips

Externí odkaz: https://explore.openaire.eu/search/publication?articleId=doi_dedup___::193ac4266570d402685601f736e49166
https://doi.org/10.1109/date.2012.6176556

Composant de traitement d'un signal numérique, dispositif de modulation et/ou de démodulation multiporteuse, procédé de modulation et/ou de démodulation et programme d'ordinateur correspondants

Autor: Callonnec, D., Pétrot, Frédéric, Sahnine, C., Zergainoh, N.

Publikováno v: France, N° de brevet: WO/2008/145915 / PCT/FR2008/050703. http://www.wipo.int/pctdb/en/wo.jsp?WO=2008145915. 2008

The invention relates to a component (81) for processing a digital signal, that comprises: an assembly (101, 111) of elementary calculation modules including a connection means; and a control unit (83) capable of configuring the connection means of a

Externí odkaz: https://explore.openaire.eu/search/publication?articleId=dedup_wf_001::26e8be8c79ab8b0d45f1b14d76f35843
https://hal.archives-ouvertes.fr/hal-00570292

IP-block-based design environment for high-throughput VLSI dedicated digital signal processing systems

Autor: Zergainoh, N.-E., Popovici, K., Jerraya, A. A., Urard, P.

Publikováno v: Asia and South Pacific Design Automation Conference (ASP-DAC'05)
Asia and South Pacific Design Automation Conference (ASP-DAC'05), Jan 2005, Shanghai, China. pp.612-618

International audience; The growing requirement on the correct design of a high performance DSP system in short time force us to use IP's in many design. In this paper, we propose an efficient IP block based design environment for high throughput VLS

Externí odkaz: https://explore.openaire.eu/search/publication?articleId=dedup_wf_001::9a5afc1aca977929ed122c907c597708
https://hal.archives-ouvertes.fr/hal-00008000

Framework for system design, validation and fast prototyping of multiprocessor SoCs

Autor: Zergainoh, N., Baghdadi, Amer, Tambour, L., Lyonnard, D., Gauthier, L., Jerraya, A.A.

Publikováno v: Architecture and Design of Distributed Embedded Systems Series: IFIP International Federation for Information Processing
Architecture and Design of Distributed Embedded Systems Series: IFIP International Federation for Information Processing, Kluwer Academic Publishers, 2001, Vol. 61

ISBN: 0-7923-7345-6; International audience; Due to the decreasing production costs of IT systems, applications that had to be realised as expensive PCBs formerly, can now be realised as a system-on-chip. Furthermore, low cost broadband communication

Externí odkaz: https://explore.openaire.eu/search/publication?articleId=dedup_wf_001::61c4a3aabe0748b2b7325b07f149890e
https://hal.archives-ouvertes.fr/hal-00016207

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