Zobrazeno 1 - 4
of 4
pro vyhledávání: '"Zen-Yi Huang"'
Publikováno v:
5th IEEE Conference on Nanotechnology, 2005..
This paper presents an Field Programmable gate Array (FPGA) integrated architecture to perform a pipelined operations of image capturing, convolution and sorting, which are usually done serially. When pixels serially coming from image sensor pile up
Externí odkaz:
https://explore.openaire.eu/search/publication?articleId=doi_________::34dbdc9837023709ac49ccf9880fb48e
https://doi.org/10.1109/nano.2005.1500749
https://doi.org/10.1109/nano.2005.1500749
Publikováno v:
5th IEEE Conference on Nanotechnology, 2005..
This paper presents a CPU design of 25 MIPS instructions in addition to the interface controller circuitries of LCD, 7-seg and key pad and all are downloaded on a 200k gate-count FPGA board for system verification. Then an image process device develo
Externí odkaz:
https://explore.openaire.eu/search/publication?articleId=doi_________::5483719dd935ccd75b02be539fe58e19
https://doi.org/10.1109/nano.2005.1500725
https://doi.org/10.1109/nano.2005.1500725
Autor:
Bebis, George, Boyle, Richard, Koracin, Darko, Parvin, Bahram, Chi-Jeng Chang, Wu-Ting Wu, Hui-Ching Su, Zen-Yi Huang, Hsin-Yen Li
Publikováno v:
Advances in Visual Computing; 2005, p672-677, 6p
Publikováno v:
5th IEEE Conference on Nanotechnology, 2005; 2005, p275-275, 1p