Zobrazeno 1 - 6
of 6
pro vyhledávání: '"Zaven M. Avetisyan"'
Autor:
V.Sh. Melikyan, Zaven M. Avetisyan, A.Kh. Mkhitaryan, Synopsys Armenia Cjsc, Artur A. Petrosyan, A.E. Mkrtchyan, Artak Hayrapetyan
Publikováno v:
Problems of advanced micro- and nanoelectronic systems development. :76-81
Autor:
V.Sh. Melikyan, Zaven M. Avetisyan, A.E. Mkrtchyan, Aristakes Hovsepyan, A.Kh. Mkhitaryan, Artur A. Petrosyan, Synopsys Armenia Cjsc, Artak Hayrapetyan
Publikováno v:
Problems of advanced micro- and nanoelectronic systems development. :63-68
Autor:
Zaven M. Avetisyan
Publikováno v:
2019 IEEE 39th International Conference on Electronics and Nanotechnology (ELNANO).
Aging-aware standard cell libraries are characterized to estimate aging impact on digital integrated circuits (IC) and to measure parameters of digital IC after degradation. In existing libraries cells are characterized considering cell’s input sig
Autor:
Armen A. Martirosyan, Vazgen Melikyan, Zaven M. Avetisyan, Manvel T. Grigoryan, Karen T. Khachikyan, Arman S. Petrosyan, Arman S. Trdatyan, Arthur S. Sahakyan
Publikováno v:
EWDTS
Transmitters' output signal correction is very important for high speed serial link standards such as Universal Serial Bus (USB), X Attachment Unit Interface (XAUI), Peripheral Component Interconnect (PCI), Double Data Rate (DDR) etc. Day by day inte
Autor:
Nune H. Beglaryan, Vardan P. Grigoryants, Zaven M. Avetisyan, Andranik K. Hayrapetyan, Simon H. Gharibyan, Artur Kh. Mkhitaryan, Vazgen Melikyan, Gegham A. Petrosyan
Publikováno v:
EWDTS
Low power, area efficient clocked comparator with high resolution was designed in SAED 32/28nm CMOS process for SAR ADC applications. The analog comparator is based on digital cells, hence doesn't have stability issues, mismatches induced by the diff
Autor:
Shavarsh V. Melikyan, Zaven M. Avetisyan, Artur A. Petrosyan, Andranik K. Hayrapetyan, Artur Kh. Mkhitaryan, Vazgen Melikyan
Publikováno v:
2018 IEEE 38th International Conference on Electronics and Nanotechnology (ELNANO).
This paper proposes a method of voltage overshoot correction during the load switching-off in the integrated circuits (ICs) where the negative feedback voltage regulators are used. Method uses fictive dynamic load to compensate the fast switching-off