Zobrazeno 1 - 10
of 272
pro vyhledávání: '"Zainalabedin Navabi"'
Autor:
Nooshin Nosrati, Zainalabedin Navabi
Publikováno v:
IEEE Access, Vol 12, Pp 52851-52866 (2024)
As Long Short-Term Memory (LSTM) accelerators are increasingly being employed in safety-critical applications with high-reliability demands, protecting them against errors becomes imperative. Traditional protection techniques for LSTMs are either cos
Externí odkaz:
https://doaj.org/article/24a94d1de94b496288aa32e81b44bbeb
Publikováno v:
IET Computers & Digital Techniques, Vol 2024 (2024)
This article proposes an efficient and accurate embedded motor imagery-based brain–computer interface (MI-BCI) that meets the requirements for wearable and real-time applications. To achieve a suitable accuracy considering hardware constraints, we
Externí odkaz:
https://doaj.org/article/488524fe637c45c29dc4b66573d41361
Publikováno v:
2022 IEEE 28th International Symposium on On-Line Testing and Robust System Design (IOLTS).
Externí odkaz:
https://explore.openaire.eu/search/publication?articleId=doi_________::468f9828783e8eb4e7cfdf85e2507715
https://doi.org/10.1109/iolts56730.2022.9897309
https://doi.org/10.1109/iolts56730.2022.9897309
Publikováno v:
2022 IEEE European Test Symposium (ETS).
Externí odkaz:
https://explore.openaire.eu/search/publication?articleId=doi_________::bfea5333395f3d9b1e48f6f4f3ea4c8e
https://doi.org/10.1109/ets54262.2022.9810369
https://doi.org/10.1109/ets54262.2022.9810369
Autor:
Mohammad Ebrahimi, Zainalabedin Navabi
Publikováno v:
IEEE Transactions on Computer-Aided Design of Integrated Circuits and Systems. 39:2976-2989
This article proposes a methodology for critical path selection and delay sensor insertion for aging monitoring in field-programmable gate arrays (FPGAs). The aging information can be used to reconfigure FPGAs to achieve better performance or wear le
Externí odkaz:
https://explore.openaire.eu/search/publication?articleId=doi_________::aad2268f5c2ec6117fe0d0a3d7940f28
https://doi.org/10.1109/tcad.2019.2953174
https://doi.org/10.1109/tcad.2019.2953174
Publikováno v:
IEEE Transactions on Computers. 69:1500-1506
In this article, we propose a fine-grained FPGA aging mitigation method. Our method focuses on Look Up Tables (LUTs) on which Boolean functions are mapped. Based on our observations, for any configuration, even if it is carefully selected, a number o
Externí odkaz:
https://explore.openaire.eu/search/publication?articleId=doi_________::d6b2590ee2e2dcf94d1670ea422542ac
https://doi.org/10.1109/tc.2020.2974955
https://doi.org/10.1109/tc.2020.2974955
Publikováno v:
IEEE Transactions on Emerging Topics in Computing. 8:627-641
Time-variant age information of different parts of a system can be used for system-level performance improvement through high-level task scheduling, thus extending the life-time of the system. Progressive age information should provide the age state
Externí odkaz:
https://explore.openaire.eu/search/publication?articleId=doi_________::1002114315024130dc7d75e7ce40e30b
https://doi.org/10.1109/tetc.2017.2771441
https://doi.org/10.1109/tetc.2017.2771441
Publikováno v:
ISVLSI
Long Short-Term Memory (LSTM) is widely adopted to recognize the dynamic behavior of many real-time sequential problems such as healthcare issues, natural language processing, and self-drive vehicles. The need for large memory and the complexity of m
Externí odkaz:
https://explore.openaire.eu/search/publication?articleId=doi_________::8c3ffea488511c22fbb233d0607b7d30
https://doi.org/10.1109/isvlsi51109.2021.00046
https://doi.org/10.1109/isvlsi51109.2021.00046
Autor:
Mahsa Akhsham, Zainalabedin Navabi
Publikováno v:
IOLTS
An online interconnect BIST for detecting and avoiding interconnect faults is proposed in this paper. This BIST structure is built upon a new shielding method, the required hardware of which is reutilized in transmitting redundant test data across th
Externí odkaz:
https://explore.openaire.eu/search/publication?articleId=doi_________::83eee26ef9326ddc8a5c0b0dae913eaf
https://doi.org/10.1109/iolts52814.2021.9486702
https://doi.org/10.1109/iolts52814.2021.9486702
Autor:
Zahra Mahdavi, Nooshin Nosrati, Zainalabedin Navabi, Katayoon Basharkhah, Hanieh Totonchi Asl
Publikováno v:
DTIS
This paper is on a RISCV-like processor and developing a virtual tester for it. We define a Virtual Tester as a testbench in an HDL that performs test functions as an automatic test equipment does. The virtual tester is used for developing test sets,
Externí odkaz:
https://explore.openaire.eu/search/publication?articleId=doi_________::54d9650ac859f9795a9987fabee41b90
https://doi.org/10.1109/dtis53253.2021.9505110
https://doi.org/10.1109/dtis53253.2021.9505110