Zobrazeno 1 - 10
of 15
pro vyhledávání: '"Zacharias Hadjilambrou"'
Publikováno v:
IEEE Transactions on Computers. 70:1338-1349
Worst-case dI/dt voltage noise is typically characterized post-silicon using direct voltage measurements through either on-package measurement points or on-chip dedicated circuitry. These approaches consume expensive pad resources or suffer from desi
Publikováno v:
ISPASS
This work reports on the results of a performance characterization of Simultaneous Multi-Threading (SMT) and Index-Partitioning (IP) when executing an online document search application. One of the key paper findings is that SMT is suitable for a lat
Publikováno v:
IEEE Journal of Solid-State Circuits
This paper presents a power delivery monitor (PDM) peripheral integrated in a flip-chip packaged 28 nm system-on-chip (SoC) for mobile computing. The PDM is composed entirely of digital standard cells and consists of: 1) a fully integrated VCO-based
Autor:
William Fornaciari, Antoni Portero, Alessandro Bacchini, Zacharias Hadjilambrou, Fritsch Agnes, Martin Golasowski, Michail Noltsis, Francky Catthoor, Panayiotis Englezakis, Stepan Kuchar, Jiri Sevcik, Giuseppe Massari, Radim Vavrik, Vít Vondrák, Hans Cappelle, Nikolaos Zompakis, Simone Libutti, Panagiota Nikolaou, Dimitrios Soudris, Yiannakis Sazeides, Chrysostomos Nicopoulos, Federico Sassi, Lorena Ndreu
Publikováno v:
Harnessing Performance Variability in Embedded and High-performance Many/Multi-core Platforms ISBN: 9783319919614
The goal of the HARPA solution is to overcome the performance variability (PV) by enabling next-generation embedded and high-performance platforms using heterogeneous many-core processors to provide cost-effectively dependable performance: the correc
Externí odkaz:
https://explore.openaire.eu/search/publication?articleId=doi_dedup___::505601376adf94b82a3e1baa09ea9ddd
http://hdl.handle.net/11311/1066938
http://hdl.handle.net/11311/1066938
Autor:
Panayiotis Englezakis, Radim Vavrik, Vít Vondrák, Zacharias Hadjilambrou, Panagiota Nikolaou, Yiannakis Sazeides, Antoni Portero, Chrysostomos Nicopoulos, Lorena Ndreu
Publikováno v:
Harnessing Performance Variability in Embedded and High-performance Many/Multi-core Platforms ISBN: 9783319919614
This chapter evaluates and defines a methodology for the oracle selection of the monitors and knobs to use to configure an HPC system running a scientific application while satisfying the application’s requirements and not violating any system cons
Externí odkaz:
https://explore.openaire.eu/search/publication?articleId=doi_________::327c4674d5be7e713b36cc919fc529b9
https://doi.org/10.1007/978-3-319-91962-1_8
https://doi.org/10.1007/978-3-319-91962-1_8
Publikováno v:
ISSCC
The current trend for System-on-Chip (SoC) compute subsystems is to improve energy efficiency, while operating at a similar power budget as previous generations. Reduced supply voltages and increased transistor density affords SoCs composed of multip
Autor:
ZONI, DAVIDE1 davide.zoni@polimi.it, GALIMBERTI, ANDREA1 andrea.galimberti@polimi.it, FORNACIARI, WILLIAM1 william.fornaciari@polimi.it
Publikováno v:
ACM Computing Surveys. 2023 Suppl14s, Vol. 55, p1-33. 33p.
Publikováno v:
IEEE Transactions on Computers; Sep2021, Vol. 70 Issue 9, p1338-1349, 12p
Electrical-Level Attacks on CPUs, FPGAs, and GPUs: Survey and Implications in the Heterogeneous Era.
Autor:
MAHMOUD, DINA G.1 dina.mahmoud@epfl.ch, LENDERS, VINCENT2 vincent.lenders@armasuisse.ch, STOJILOVIĆ, MIRJANA1 mirjana.stojilovic@epfl.ch
Publikováno v:
ACM Computing Surveys. Apr2023, Vol. 55 Issue 3, p1-40. 40p.
Publikováno v:
IEEE Computer Architecture Letters; Jan/Jun2018, Vol. 17 Issue 1, p68-71, 4p