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Autor: R. Matousek, N.F. Benschop, J.N. Coleman, A. Hermanek, Milan Tichy, C.I. Softley, Jiri Kadlec, Z. Pohl

Publikováno v: IEEE Transactions on Computers. 57:532-546

In 2000 we described a proposal for a logarithmic arithmetic unit, which we suggested would offer a faster, more accurate alternative to floating-point procedures. Would it in fact do so, and could it feasibly be integrated into a microprocessor so t

Externí odkaz: https://explore.openaire.eu/search/publication?articleId=doi_________::12d4a790ab4326455b76cbdbf0ff968e
https://doi.org/10.1109/tc.2007.70791

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Pollution performance of 110 kV metal oxide arresters

Autor: K. Chrzan, Stanislaw Grzybowski, Z. Pohl, W. Kohler

Publikováno v: IEEE Transactions on Power Delivery. 12:728-733

Pollution test results of single-unit 110 kV metal oxide surge arresters with porcelain housing according to the solid layer and salt fog methods are presented. During 6 hours of testing, the internal and external charge and maximum temperature along

Externí odkaz: https://explore.openaire.eu/search/publication?articleId=doi_________::b3e9a50d3366f8622981b200588a2d7c
https://doi.org/10.1109/61.584358

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Performance tuning of iterative algorithms in signal processing

Autor: Jiri Kadlec, P. Sucha, Z. Pohl, Z. Hanzdlek

Publikováno v: FPL

Presented high-level synthesis describes scheduling for wide class of DSP algorithms. Several FPGA vendors or even ASIC designs are targeted via Handel-C compiled by Celoxica DK3.1 compiler. Using the authors' approach, the designer can easily change

Externí odkaz: https://explore.openaire.eu/search/publication?articleId=doi_________::a8287c8ac7cebd53ef0c2289201b511a
https://doi.org/10.1109/fpl.2005.1515816

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Figaro - an automatic tool flowfor designs with dynamic reconfiguration

Autor: M. Danek, K. Nasi, Z. Pohl, T. Karouhalis

Publikováno v: FPL

Although runtime partial dynamic reconfiguration of FPGAs has been researched for many years and there have been a few FPGAs equipped with the required architectural features, it has yet to achieve general recognition by the commercial design communi

Externí odkaz: https://explore.openaire.eu/search/publication?articleId=doi_________::7da5a7fe3988353992bffb4afc2eb1cc
https://doi.org/10.1109/fpl.2005.1515792

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Scheduling of iterative algorithms on FPGA with pipelined arithmetic unit

Autor: Zdenek Hanzalek, Z. Pohl, P. Sucha

Publikováno v: IEEE Real-Time and Embedded Technology and Applications Symposium
Scopus-Elsevier

This paper presents a scheduling technique for a library of arithmetic logarithmic modules for FPGA illustrated on a RLS filter for active noise cancellation. The problem under assumption is to find an optimal periodic cyclic schedule satisfying the

Externí odkaz: https://explore.openaire.eu/search/publication?articleId=doi_dedup___::c0f81526bb3edd24da7f40bd2f68b32c
https://doi.org/10.1109/rttas.2004.1317287

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The European Logarithmic Microprocessor - a QR RLS application

Autor: J.N. Coleman, C.I. Softley, Jiri Kadlec, Z. Pohl, A. Hermanek, M. Licko, R. Matousek

Publikováno v: Conference Record of Thirty-Fifth Asilomar Conference on Signals, Systems and Computers (Cat.No.01CH37256).

In contrast to all other microprocessors, which use floating-point for their real arithmetic, the European Logarithmic Microprocessor is the world's first device to use the logarithmic number system for this purpose. Simulation work has already sugge

Externí odkaz: https://explore.openaire.eu/search/publication?articleId=doi_________::8bc84dee345b909b0da5f521e5568b11
https://doi.org/10.1109/acssc.2001.986897

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