Zobrazeno 1 - 10
of 90
pro vyhledávání: '"Yuzo Takamatsu"'
Publikováno v:
IPSJ Transactions on System LSI Design Methodology. 2:250-262
Conventional stuck-at fault model is no longer sufficient to deal with the problems of nanometer geometries in modern Large Scale Integrated Circuits (LSIs). Test and diagnosis for transistor defects are required. In this paper we propose a fault dia
Externí odkaz:
https://explore.openaire.eu/search/publication?articleId=doi_________::378a17b6016af3f3b361b8ab27ea9bd6
https://doi.org/10.2197/ipsjtsldm.2.250
https://doi.org/10.2197/ipsjtsldm.2.250
Publikováno v:
IEICE Transactions on Fundamentals of Electronics, Communications and Computer Sciences. :3128-3135
Shorts and opens are two major kind of defects that are most likely to occur in Very Large Scale Integrated Circuits. In modern Integrated Circuit devices these defects must be considered not only at gate-level but also at transistor level. In this p
Externí odkaz:
https://explore.openaire.eu/search/publication?articleId=doi_________::7b2397fe73d23c0d8e4dfdd46e8166f5
https://doi.org/10.1587/transfun.e92.a.3128
https://doi.org/10.1587/transfun.e92.a.3128
Publikováno v:
IEICE Transactions on Fundamentals of Electronics, Communications and Computer Sciences. :3506-3513
Physical defects that are not covered by stuck-at fault or bridging fault model are increasing in LSI circuits designed and manufactured in modern Deep Sub-Micron (DSM) technologies. Therefore, it is necessary to target non-stuck-at and non-bridging
Externí odkaz:
https://explore.openaire.eu/search/publication?articleId=doi_________::f44af483c96ed100ee1cbf55c8f4a754
https://doi.org/10.1093/ietfec/e91-a.12.3506
https://doi.org/10.1093/ietfec/e91-a.12.3506
Publikováno v:
IEICE Transactions on Information and Systems. :690-699
This paper presents methods for detecting transistor short faults using logic level fault simulation and test generation. The paper considers two types of transistor level faults, namely strong shorts and weak shorts, which were introduced in our pre
Externí odkaz:
https://explore.openaire.eu/search/publication?articleId=doi_________::129a39bc60d2b91cb85b602fcaae66d9
https://doi.org/10.1093/ietisy/e91-d.3.690
https://doi.org/10.1093/ietisy/e91-d.3.690
Autor:
Koji Yamazaki, Y. Sato, Hiroshi Takahashi, Yuzo Takamatsu, Yoshinobu Higami, Takashi Aikyo, Shuhei Kadoyama
Publikováno v:
IEICE Transactions on Information and Systems. :771-775
With the increasing complexity of LSI, Built-In Self Test (BIST) is a promising technique for production testing. We herein propose a method for diagnosing multiple stuck-at faults based on the compressed responses from BIST. We refer to fault diagno
Externí odkaz:
https://explore.openaire.eu/search/publication?articleId=doi_________::b6f27e629ece7d0fd9a6d52886805ce7
https://doi.org/10.1093/ietisy/e91-d.3.771
https://doi.org/10.1093/ietisy/e91-d.3.771
Publikováno v:
IEICE Transactions on Information and Systems. :675-682
In general, we do not know which fault model can explain the cause of the faulty values at the primary outputs in a circuit under test before starting diagnosis. Moreover, under Built-In Self Test (BIST) environment, it is difficult to know which pri
Externí odkaz:
https://explore.openaire.eu/search/publication?articleId=doi_________::b3b1f9e19e96402985930516989b4b76
https://doi.org/10.1093/ietisy/e91-d.3.675
https://doi.org/10.1093/ietisy/e91-d.3.675
Autor:
Yuzo Takamatsu, Koji Yamazaki
Publikováno v:
IEICE Transactions on Information and Systems. :661-666
In order to reduce the test cost, built-in self test (BIST) is widely used. One of the serious problems of BIST is that the compacted signature in BIST has very little information for fault diagnosis. Especially, it is difficult to determine which te
Externí odkaz:
https://explore.openaire.eu/search/publication?articleId=doi_________::71a594f36291e6580ca797a576845fed
https://doi.org/10.1093/ietisy/e91-d.3.661
https://doi.org/10.1093/ietisy/e91-d.3.661
Publikováno v:
IEICE Transactions on Information and Systems. :2748-2755
Recently there are various requirements for LSI testing, such as test compaction, test compression, low power dissipation or increase of defect coverage. If test sequences contain lots of don't cares (Xs), then their flexibility can be used to meet t
Externí odkaz:
https://explore.openaire.eu/search/publication?articleId=doi_________::c6642b0b933f11fe586c74811ca2e7c1
https://doi.org/10.1093/ietisy/e89-d.11.2748
https://doi.org/10.1093/ietisy/e89-d.11.2748
Publikováno v:
IEEE Transactions on Computer-Aided Design of Integrated Circuits and Systems. 24:252-263
We describe a method of identifying a set of target crosstalk faults which may need to be tested in synchronous sequential circuits. Our method classifies the pairs of aggressor and victim lines, using topological and timing information, to deduce a
Externí odkaz:
https://explore.openaire.eu/search/publication?articleId=doi_________::774a18516cf59fff457535ce4985df1a
https://doi.org/10.1109/tcad.2004.837733
https://doi.org/10.1109/tcad.2004.837733
Publikováno v:
Systems and Computers in Japan. 36:69-83
Externí odkaz:
https://explore.openaire.eu/search/publication?articleId=doi_________::7ffd79903113e2bf748152a3e6060e52
https://doi.org/10.1002/scj.20240
https://doi.org/10.1002/scj.20240