Zobrazeno 1 - 10
of 14
pro vyhledávání: '"Yuzo Fukuzaki"'
Autor:
Manabu Tomita, Tsuyoshi Suzuki, Kazuhisa Ogawa, Hidetoshi Oishi, Masaaki Bairo, Yuzo Fukuzaki, Hidetoshi Ohnuma, Shigetaka Mori
Publikováno v:
IEEE Transactions on Semiconductor Manufacturing. 29:185-192
A novel monitoring test structure is proposed for plasma process-induced charging damage (PID) based on charge-based capacitance measurement (CBCM), referred to as PID–CBCM. By eliminating antenna capacitance interferences, a remarkably smaller gat
Autor:
Ken Sawada, Tsuyoshi Suzuki, Manabu Tomita, Shigetaka Mori, Hidetoshi Oishi, Hidetoshi Ohnuma, Yuzo Fukuzaki, Kazuhisa Ogawa, Masaaki Bairo
Publikováno v:
2016 International Conference on Microelectronic Test Structures (ICMTS).
A highly effective and versatile test structure with a flexible pulse generating circuit is proposed. Several significant features of the key components are demonstrated, that is, the tunable ring oscillator, the start-stop pulse controller, the Char
Autor:
Yuzo Fukuzaki, Masaaki Bairo, Hidetoshi Oishi, Kazuhisa Ogawa, Shigetaka Mori, Tsuyoshi Suzuki, Hidetoshi Ohnuma, Manabu Tomita
Publikováno v:
2016 International Conference on Microelectronic Test Structures (ICMTS).
A Novel Ioff measurable MOSFET array has been developed. Body bias of peripheral circuit is controlled in order to eliminate the unwanted leakage current in peripheral circuit. SPICE simulation results indicate 10−14A or less of Ioff can be measure
Autor:
Carlo Cagli, Yuzo Fukuzaki
Publikováno v:
2016 International Conference on Microelectronic Test Structures (ICMTS).
Autor:
Yuzo Fukuzaki, Hidetoshi Ohnuma, Manabu Tomita, Hidetoshi Oishi, Shigetaka Mori, Kazuhisa Ogawa, Tsuyoshi Suzuki, Masaaki Bairo
Publikováno v:
Proceedings of the 2015 International Conference on Microelectronic Test Structures.
We propose monitoring test structure and measurement technique for plasma process induced charging damage (PID) using charge-based capacitance measurement (CBCM). For evaluating the influence of PID on MOSFET effectively, remarkably small (several te
Autor:
Hiroaki Ammo, Shigetaka Mori, Yuzo Fukuzaki, Verkest Diederik, Ken Sawada, Cherman Vladimir, Abdelkarim Mercha, Geert Van der Plas
Publikováno v:
Proceedings of the 2015 International Conference on Microelectronic Test Structures.
CBCM measurements require known clock frequency. We proposed CBCM test structures with an internal start-stop self-pulsing circuit instead of external clock monitoring.
Autor:
Vladimir Cherman, Tsuyoshi Suzuki, Julien Ryckaert, Eric Beyne, Shigetaka Mori, Ankur Anchlia, Hidetoshi Ohnuma, Hidetoshi Oishi, Diederik Verkest, Yuzo Fukuzaki, Geert Van der Plas, Kazuhisa Ogawa
Publikováno v:
Proceedings of the 2015 International Conference on Microelectronic Test Structures.
We have successfully developed the new design of MOSFET array structure with high accuracy measurement both for Ion excluding IR drop and Ioff without contamination. We propose measurement algorithm “feedback looped biasing” with kelvin probe str
Autor:
SungGeun Kim, Yuzo Fukuzaki, Charles Cheung, Mustafa Badaroglu, Mehdi Salmani, Kwok Ng, Gerhard Klimeck, Chorng-Ping Chang
Publikováno v:
ICCD
CMOS scaling enabled simultaneous system throughput scaling by concurrent delay, power, and area shrinks with thanks to Moore's law. System scaling is getting more difficult with the limitations in interconnect and bandwidth per power as well as the
Autor:
M. Kanno, A. Shibuya, K. Tamura, H. Ansai, S. Mori, T. Gocho, Naoki Nagashima, Yuzo Fukuzaki, M. Matsumura, H. Tsuno
Publikováno v:
2007 IEEE Symposium on VLSI Technology.
This paper proposes a practical methodology to extract overall variations of MOSFET characteristics on 65nm node and beyond. Firstly, we show how MOSFET variations are originated and categorized by these causes and unit regions. Secondly, we demonstr
Autor:
M. Matsumura, H. Koike, Y. Hiura, M. Kanno, A. Honjo, K. Anzai, Yuzo Fukuzaki, H. Tsuno, A. Takeo, H. Ansai, Naoki Nagashima, S. Minami, W. Fu
Publikováno v:
2007 IEEE Symposium on VLSI Technology.
We report an advanced method of analyzing and modeling MOSFET characteristic fluctuations in CMOS circuits. We focused on gate space dependence, STI width dependence, and interaction between gate-STI distance and STI width in 65-nm node technology wi