Zobrazeno 1 - 7
of 7
pro vyhledávání: '"Yuta Toriyama"'
Autor:
Dejan Markovic, Yuta Toriyama
Publikováno v:
IEEE Journal of Solid-State Circuits. 53:2378-2388
Non-binary low-density parity-check (NB-LDPC) codes are a promising class of error-correcting codes that provide excellent coding gain beyond that of their binary counterparts. However, their decoding complexity has thus far limited practicality. We
Externí odkaz:
https://explore.openaire.eu/search/publication?articleId=doi_________::4410fc42c59d702291cb6e4c38e4fa93
https://doi.org/10.1109/jssc.2018.2832851
https://doi.org/10.1109/jssc.2018.2832851
Autor:
Yuta Toriyama, Dejan Markovic
Publikováno v:
2017 Symposium on VLSI Circuits.
This paper presents a Non-Binary LDPC decoder with information throughput of 2.267Gbps and power consumption of 212.4mW, yielding an energy efficiency of 93.7pJ/b, implemented in a 40nm CMOS technology. The employed code is long and high-rate without
Externí odkaz:
https://explore.openaire.eu/search/publication?articleId=doi_________::4b9dd81752e5c82dcead9b3498d427c3
https://doi.org/10.23919/vlsic.2017.8008530
https://doi.org/10.23919/vlsic.2017.8008530
Autor:
Dejan Markovic, Chih-Kong Ken Yang, Yuta Toriyama, Fengbo Ren, Richard Dorrance, Amr Amin Hafez
Publikováno v:
IEEE Transactions on Electron Devices. 59:878-887
We present a design-space feasibility region, as a function of magnetic tunnel junction (MTJ) characteristics and target memory specifications, to explore the design margin of a one-transistor-one-magnetic-tunnel-junction (1T-1MTJ) memory cell for sp
Externí odkaz:
https://explore.openaire.eu/search/publication?articleId=doi_________::81265c77691fc459becfe75092f7d3c1
https://doi.org/10.1109/ted.2011.2182053
https://doi.org/10.1109/ted.2011.2182053
Publikováno v:
GLOBECOM
Non-binary low-density parity-check (NB-LDPC) codes exhibit excellent error correction performance at the cost of high computational complexity of the decoding algorithm. A logarithmic quantization scheme is proposed to reduce the VLSI implementation
Externí odkaz:
https://explore.openaire.eu/search/publication?articleId=doi_________::bae3234209d06e231b3c2cec3fb232f2
https://doi.org/10.1109/glocom.2014.7037292
https://doi.org/10.1109/glocom.2014.7037292
Publikováno v:
ACSSC
Non-binary low-density parity-check codes exhibit excellent coding gain at the cost of decoding complexity. Furthermore, the effects of the Galois field order on the hardware cost have not been well established. We propose a modification to the Min-M
Externí odkaz:
https://explore.openaire.eu/search/publication?articleId=doi_________::ea881cd791989df957965ffdfd23f2dd
https://doi.org/10.1109/acssc.2014.7094832
https://doi.org/10.1109/acssc.2014.7094832
Publikováno v:
ISQED
With scaling of CMOS and Magnetic Tunnel Junction (MTJ) devices, conventional low-current reading techniques for STT-RAMs face challenges in achieving reliability and performance improvements that are expected from scaled devices. The challenges aris
Externí odkaz:
https://explore.openaire.eu/search/publication?articleId=doi_________::ee6b9228fe5df2aa7d90cc0cd1995fa2
https://doi.org/10.1109/isqed.2012.6187506
https://doi.org/10.1109/isqed.2012.6187506
Publikováno v:
NANOARCH
This paper introduces a design-space feasibility region as a function of MTJ characteristics and memory target specifications. The sensitivity of the design space is analyzed for scaling of both MTJ and underlying transistor technology. Design points
Externí odkaz:
https://explore.openaire.eu/search/publication?articleId=doi_________::1cd7c21c1b423833b5a210b3c8317162
https://doi.org/10.1109/nanoarch.2011.5941480
https://doi.org/10.1109/nanoarch.2011.5941480