Zobrazeno 1 - 10
of 24
pro vyhledávání: '"Yusuke, Oniki"'
Autor:
Efrain Altamirano Sanchez, Herbert Struyf, Tatsunobu Suzuki, Frank Holsteyns, Yusuke Oniki, Ken Harada, Kan Takeshita, Tomohiro Kusano
Publikováno v:
Solid State Phenomena. 314:71-76
3 formulated etchants were prepared and their etch rates were measured using blanket wafers in order to confirm that the etching reactions on Si1-XGeX and Si are controllable. Si1-XGeX selective etching with those formulations was also verified using
Autor:
Harold Dekkers, Frank Holsteyns, Lars-Ake Ragnarsson, Naoto Horiguchi, Boon Teik Chan, Hideaki Iino, Yusuke Oniki, Daire J. Cott, Efrain Altamirano Sanchez, Toby Hopf, Farid Sebaai, Eugenio Dentoni Litta
Publikováno v:
Solid State Phenomena. 314:119-126
This paper addresses challenges and solutions of replacement metal gate of gate-all-around nanosheet devices. The unit process and integration solutions for the metal gate patterning as well as interface dipole patterning to offer multiple threshold
Autor:
Naoto Horiguchi, Basoene Briggs, Boon Teik Chan, Steven Demuynck, Maryam Hosseini, Geert Mannaert, Hans Mertens, Yusuke Oniki, Sujith Subramanian, Zheng Tao
Publikováno v:
Advanced Etch Technology and Process Integration for Nanopatterning XI.
Autor:
Yusuke Muraki, Yusuke Oniki, Pallavi P. Gowda, Efrain Altamirano-Sánchez, Hans Mertens, Naoto Horiguchi, Frank Holsteyns, Subhadeep Kal, Cheryl Alix, Kaushik Kumar, Aelan Mosden, Trace Hurd, Nobuyuki Takahashi
Publikováno v:
Advanced Etch Technology and Process Integration for Nanopatterning XI.
Autor:
Kawarazaki, Hikaru, Nakano, Teppei, Ishizu, Takaaki, Tanaka, Takayoshi, Liu, Wen, Chen, Jason, Kawashima, Tomohiko, Wu, Ai Ping, Sebaai, Farid, Lai, Ju Geng, Yusuke, Oniki, Altamirano-Sanchez, Efrain
Publikováno v:
Diffusion and Defect Data Part B: Solid State Phenomena; August 2023, Vol. 346 Issue: 1 p23-28, 6p
Publikováno v:
ECS Transactions. 92:3-12
This paper addresses the opportunities and challenges of wet and dry selective etches in the integration of gate-all-around (GAA) field-effect transistor (FET), which is emerging as a promising solution to replace FinFET for the advanced logic device
Autor:
Philippe Leray, Valentina Spampinato, R. Koret, Alain Moussa, Ilse Hoflijk, J. Hung, Y. Muraki, Thomas Nuytten, Janusz Bogdanowicz, Johan Meersschaut, Alexis Franquet, Stefanie Sergeant, Yusuke Oniki, N. Claessens, Thierry Conard, Karine Kenis, Anne-Laure Charley, D. Van den Heuvel
Publikováno v:
Metrology, Inspection, and Process Control for Semiconductor Manufacturing XXXV.
Nanosheet Field-Effect Transistors (FETs) are candidates to replace today’s finFETs as they offer both an enhanced electrostatic control and a reduced footprint. The processing of these devices involves the selective lateral etching, also called ca
Autor:
Subhadeep Kal, Karine Kenis, Trace Hurd, Yusuke Muraki, Peter Biolsi, Cheryl Alix, Aelan Mosden, Naoto Horiguchi, Yusuke Oniki, Frank Holsteyns, Kaushik A. Kumar, Efrain Altamirano-Sánchez, Chanemougame Daniel
Publikováno v:
Advanced Etch Technology for Nanopatterning IX.
R&D on transistor fabrication and scaling for current and future technology nodes involves various 3D-device architectures like the established finFET (fin “Field Effect Transistor”), and newer architectures like GAA (Gate All Around) which may i
Autor:
Guy Vereecke, Naoto Horiguchi, Lars-Ake Ragnarsson, Eugenio Dentoni Litta, Yusuke Oniki, Tom Schram, Harold Dekkers, Frank Holsteyns
Publikováno v:
Solid State Phenomena. 282:132-138
A self-limiting wet etching of metal thin films has been developed for the replacement metal gate patterning in advanced logic devices, which will have aggressively scaled gate length and fin pitches. A uniform and highly selective wet etching of pol
Autor:
Juergen Boemmels, Qi Wang, Subhadeep Kal, Frank Holsteyns, Trace Q. Hurd, Matthew Falugh, Aelan Mosden, Cheryl Pereira, Yusuke Oniki, Kaushik A. Kumar, Julien Ryckaert, Jeffrey Smith, Peter Biolsi
Publikováno v:
Advanced Etch Technology for Nanopatterning VIII.
Area scaling without compromising on performance has become a challenge for technology nodes beyond N7. Gate all-around (GAA) device architecture for N5 and beyond technology nodes is emerging as a promising solution and is being heavily investigated