Zobrazeno 1 - 10
of 18
pro vyhledávání: '"Yuri Tkachev"'
Autor:
Xinwang Liu, Tom Herrmann, G. Festes, B. Bertello, Yuri Tkachev, Boris Bayha, M. Duggan, Ralf Richter, Alban Zaka, Decobert Catherine, Thomas Melde, S. Wittek, Stefan Dunkel, N. Do, P. Ghazav, N. Bollon, F. Mauersberger, Sven Beyer, Kim Jinho, Viktor Markov, B. Muller, Zhou Feng, S. Jourba, M. Trentzsch
Publikováno v:
2020 IEEE International Memory Workshop (IMW).
This paper presents the characterization and reliability results achieved on 1.8 V 4 Mb flash array built around 3rd generation Embedded SuperFlash® (ESF3) memory cell featuring high-k metal gate (HKMG) select transistor and embedded into Low-Power
Externí odkaz:
https://explore.openaire.eu/search/publication?articleId=doi_________::68d6b99bb8692b55d9511f87f7674fd4
https://doi.org/10.1109/imw48823.2020.9108118
https://doi.org/10.1109/imw48823.2020.9108118
Autor:
Alexander Kotov, Yuri Tkachev
Publikováno v:
Microelectronic Engineering. 178:71-75
Using a test structure containing two memory cells with a shared floating gate (FG), we analyzed the processes of hot-electron-induced charge trapping in the FG oxide with a single-trap resolution. Unlike the traditional RTN-based method for single-t
Externí odkaz:
https://explore.openaire.eu/search/publication?articleId=doi_________::eb6159937e46adb4e53dc12f37bd95ad
https://doi.org/10.1016/j.mee.2017.04.034
https://doi.org/10.1016/j.mee.2017.04.034
Autor:
Trinh Stephen T, Zhou Feng, Yuri Tkachev, Hong Stanley, Lemke Steven, Thuan Vu, N. Do, L. Tee, Xinwang Liu, Anh Ly, Hieu Van Tran, S. Jourba, Reiten Mark, Parviz Ghazavi, Decobert Catherine, Tiwari Vipin, B. Villard, Kim Jinho
Publikováno v:
2019 IEEE 11th International Memory Workshop (IMW).
In this paper, scaling prospects and challenges of embedded split-gate Superflash® (ESF) technology to 28 nm and below are discussed. The integration of the inherent HKMG in the select transistor of the split-gate memory cell ESF3 enhances the cell
Externí odkaz:
https://explore.openaire.eu/search/publication?articleId=doi_________::2e8804731d69b1b9b392af9e4b67cabb
https://doi.org/10.1109/imw.2019.8739270
https://doi.org/10.1109/imw.2019.8739270
Autor:
Jeoung Mo Koo, Soh Yun Siah, Mandana Tadayoni, Liz Cuevas, Joseph Norman, Lemke Steven, Henry Nguyen, Sheng-Hsiung Hsueh, Ee Ee Yeoh, Kok Foong Chong, Shiang Yang Ong, Namchil Mun, Hung Chang Liao, Yuri Tkachev, Zin Tun Thant, Xiaobo Ma, Jianbo Zhou, Ke Dong, Bai Yen Nguyen, Zhongxiu Yang, Huihua Jiang
Publikováno v:
2019 Electron Devices Technology and Manufacturing Conference (EDTM).
In this work we successfully integrated the split-gate SuperFlash® ESF1 cell into our 130nm BCD (Bipolar-CMOS-DMOS) platform for automotive applications. The platform enhances the modularity of flash macro in addition to logic devices, high performa
Externí odkaz:
https://explore.openaire.eu/search/publication?articleId=doi_________::eb52fbda73767a8978296413bf23626b
https://doi.org/10.1109/edtm.2019.8731154
https://doi.org/10.1109/edtm.2019.8731154
Autor:
Johannes Müller, El Mehdi Bazizi, Jochen Poth, Tom Herrmann, Hoon Kim, K. Mothes, Boris Bayha, Stefan Dunkel, Alban Zaka, Kim Jinho, N. Do, Lemke Steven, Henry A. O'm'mani, Martin Mazur, R. Huselitz, Peter Krottenthaler, Sven Beyer, S. Jansen, Parviz Ghazavi, M. Trentzsch, A. Henke, Zhou Feng, Xinwang Liu, P. Moll, Jan Paul, Yuri Tkachev, Tiwari Vipin, Ralf Richter
Publikováno v:
2018 IEEE International Electron Devices Meeting (IEDM).
We demonstrate for the first time the integration of the proven SuperFlash® bit cell into 28 nm High-K Metal Gate (HKMG) technology, incorporating logic HKMG into the flash cell. Flash cell and high-voltage (HV) devices are implemented into a cost-o
Externí odkaz:
https://explore.openaire.eu/search/publication?articleId=doi_________::1f87d0d5543f568cc29c20e10141511f
https://doi.org/10.1109/iedm.2018.8614652
https://doi.org/10.1109/iedm.2018.8614652
Publikováno v:
2018 IEEE International Memory Workshop (IMW).
We performed a comprehensive analysis of the voltage-to-erase (Verase) distribution in SST ESF3 split-gate flash memory cell arrays. It was shown that Verase distribution is mostly determined by the tunneling voltage variations. Other factors, such a
Externí odkaz:
https://explore.openaire.eu/search/publication?articleId=doi_________::5931f780e09c2c4b1896e963967ca5b7
https://doi.org/10.1109/imw.2018.8388855
https://doi.org/10.1109/imw.2018.8388855
Autor:
James Walls, Yuri Tkachev
Publikováno v:
2017 IEEE International Integrated Reliability Workshop (IIRW).
The new experimental evidence of field-induced trap generation in the tunnel oxide of SuperFlash® memory cells has been presented. It was shown that the negative voltage stress generates the highest local electric field in the oxide close to the flo
Externí odkaz:
https://explore.openaire.eu/search/publication?articleId=doi_________::8f32189d88bb5beac7ce42ec744a819b
https://doi.org/10.1109/iirw.2017.8361238
https://doi.org/10.1109/iirw.2017.8361238
Autor:
Rui Zhang, Giovanni Verzellesi, Giuseppina Puzzilli, Katja Puschkarsky, Charles LaRow, Alexander Shluger, Yuri Tkachev, Marco A. Villena, Kexin Yang, Elnatan Metaev, Milan Pesic, Jim Lloyd, Matt Ring, Peter Paliwoda, Sheldon Tan, Chadwin Young
Publikováno v:
2017 IEEE International Integrated Reliability Workshop (IIRW).
• The deep collaboration between the experimental and simulation groups is needed. • This collaboration require that: • Experimental groups should previously know what kind of information the simulations could provide and what information the s
Externí odkaz:
https://explore.openaire.eu/search/publication?articleId=doi_________::1eeebcf4b2b572d8082e88ed58cdc082
https://doi.org/10.1109/iirw.2017.8361248
https://doi.org/10.1109/iirw.2017.8361248
Autor:
Yuri Tkachev, Alexander Kotov
Publikováno v:
2017 IEEE International Memory Workshop (IMW).
Using the precisely measured floating gate capacitance, we were able to extract the absolute values of programming efficiency in the 40-nm SuperFlash® memory cells at different voltage and temperature conditions. Due to the split-gate design, the ce
Externí odkaz:
https://explore.openaire.eu/search/publication?articleId=doi_________::de43c7b9c08aa13a913aa05a78efb960
https://doi.org/10.1109/imw.2017.7939069
https://doi.org/10.1109/imw.2017.7939069
Autor:
Yuri Tkachev
Publikováno v:
2016 International Conference on Microelectronic Test Structures (ICMTS).
A new fast and simple method for extraction of capacitive coupling coefficients in a split-gate flash memory cell is described. The method is based on the modulation of cell's erase characteristics by the bias applied to the gates during read and era
Externí odkaz:
https://explore.openaire.eu/search/publication?articleId=doi_________::33ff3af5405509b7ee89c908bf65b90b
https://doi.org/10.1109/icmts.2016.7476186
https://doi.org/10.1109/icmts.2016.7476186