Zobrazeno 1 - 10
of 263
pro vyhledávání: '"Yung-Chun Wu"'
Autor:
Yi-Wen Lin, Shan-Wen Lin, Bo-An Chen, Chong-Jhe Sun, Siao-Cheng Yan, Guang-Li Luo, Yung-Chun Wu, Fu-Ju Hou
Publikováno v:
IEEE Journal of the Electron Devices Society, Vol 11, Pp 480-484 (2023)
In this study, we propose a self-aligned stacked Ge nanowire (NW) p-type gate-all-around field-effect transistor (pGAAFET) on Si nFinFET of single gate complementary FET (CFET). The self-aligned stacked Ge NW pGAAFET on Si nFinFET of single gate CFET
Externí odkaz:
https://doaj.org/article/3577e1f2e6c947749d4160e51b7f0709
Autor:
Chong-Jhe Sun, Yi-Ju Yao, Siao-Cheng Yan, Yi-Wen Lin, Shan-Wen Lin, Fu-Ju Hou, Guang-Li Luo, Yung-Chun Wu
Publikováno v:
IEEE Journal of the Electron Devices Society, Vol 10, Pp 408-412 (2022)
We investigated the ferroelectric properties of self-induced HfGeOx in a HfO2 film deposited on a SiGe substrate and analyzed a novel ferroelectric inverted T channel gate-all-around (IT-GAA) with a Si/SiGe bilayer channel and self-induced ferroelect
Externí odkaz:
https://doaj.org/article/311a0af233af47548e8ad89f5cbad34c
Autor:
Yi-Ju Yao, Ching-Ru Yang, Ting-Yu Tseng, Heng-Jia Chang, Tsai-Jung Lin, Guang-Li Luo, Fu-Ju Hou, Yung-Chun Wu, Kuei-Shu Chang-Liao
Publikováno v:
Nanomaterials, Vol 13, Iss 8, p 1310 (2023)
This research presents the optimization and proposal of P- and N-type 3-stacked Si0.8Ge0.2/Si strained super-lattice FinFETs (SL FinFET) using Low-Pressure Chemical Vapor Deposition (LPCVD) epitaxy. Three device structures, Si FinFET, Si0.8Ge0.2 FinF
Externí odkaz:
https://doaj.org/article/11ad4df17621417882231b9b58c1ba8e
Autor:
Siao-Cheng Yan, Chong-Jhe Sun, Meng-Ju Tsai, Lun-Chun Chen, Mu-Shih Yeh, Chien-Chang Li, Yao-Jen Lee, Yung-Chun Wu
Publikováno v:
IEEE Journal of the Electron Devices Society, Vol 8, Pp 589-593 (2020)
Germanium is a promising alternative material for use in advanced technology nodes because it exhibits symmetrical mobility of holes and electrons. Embedded nonvolatile memory (NVM) is essential in electronic devices with integrated circuit (IC) tech
Externí odkaz:
https://doaj.org/article/a389f55f76de47b99c14bd024bcaea31
Autor:
Chong-Jhe Sun, Meng-Ju Tsai, Siao-Cheng Yan, Tzu-Ming Chu, Chieng-Chung Hsu, Chun-Lin Chu, Guang-Li Luo, Yung-Chun Wu
Publikováno v:
IEEE Journal of the Electron Devices Society, Vol 8, Pp 1016-1020 (2020)
We successfully fabricate the Si0.8Ge0.2 channel fin field-effect-transistor (FinFET) with 5 nm ultra-thin fin width and high aspect ratio (~10×) on silicon-on-insulator (SOI) substrate by simple two-step dry etching. In comparison of the convention
Externí odkaz:
https://doaj.org/article/816ae23d20c941b8b184586460b00d2c
Autor:
Chong-Jhe Sun, Chen-Han Wu, Yi-Ju Yao, Shan-Wen Lin, Siao-Cheng Yan, Yi-Wen Lin, Yung-Chun Wu
Publikováno v:
Nanomaterials, Vol 12, Iss 20, p 3712 (2022)
We have demonstrated the method of threshold voltage (VT) adjustment by controlling Ge content in the SiGe p-channel of N1 complementary field-effect transistor (CFET) for conquering the work function metal (WFM) filling issue on highly scaled MOSFET
Externí odkaz:
https://doaj.org/article/cf02dd4bb6654330b7047944a69af126
Autor:
Meng-Ju Tsai, Kang-Hui Peng, Chong-Jhe Sun, Siao-Cheng Yan, Chieng-Chung Hsu, Yu-Ru Lin, Yu-Hsien Lin, Yung-Chun Wu
Publikováno v:
IEEE Journal of the Electron Devices Society, Vol 7, Pp 1133-1139 (2019)
Present work demonstrates the vertically double stacked nanosheet (NS) p-channel polycrystalline silicon (poly-Si) junctionless field-effect transistors (JL-FET) with tri-gate, omega-gate, and gate all around (GAA) structure. These structures offer m
Externí odkaz:
https://doaj.org/article/beb36e72cf9342389ae6efc9c2f0a9f8
Publikováno v:
IEEE Journal of the Electron Devices Society, Vol 7, Pp 1033-1037 (2019)
In this study, ferroelectric Fin field effect transistors (Fe-FinFET) with 5-nm-thick Hf0.5Zr0.5O2 (HZO) layers on silicon-on-insulator substrates were experimentally demonstrated. These devices had completed dimensions of single channel widths (WCh)
Externí odkaz:
https://doaj.org/article/d1e0bc20caa44c6f9d618454f20485eb
Autor:
Lun-Chun Chen, Hung-Bin Chen, Yu-Shuo Chang, Shih-Han Lin, Ming-Hung Han, Jia-Jiun Wu, Mu-Shih Yeh, Yu-Ru Lin, Yung-Chun Wu
Publikováno v:
IEEE Journal of the Electron Devices Society, Vol 7, Pp 168-173 (2019)
A low-voltage programmable gate-all-around (GAA) nanosheet poly-Si thin-film transistor (TFT) nonvolatile memory (NVM), which uses band-to-band tunneling induced hot electron (BBHE) programming, is demonstrated. The BBHE method is extremely efficient
Externí odkaz:
https://doaj.org/article/3a16f88ca06c45609218901b2951549b
Publikováno v:
IEEE Journal of the Electron Devices Society, Vol 7, Pp 969-972 (2019)
As technology develops, the stacked nanosheet (NS) structure demonstrates promise for use in future technology nodes. This study demonstrated the excellent performance of stacked-NS channels with junctionless gate-all-around thin-film transistors and
Externí odkaz:
https://doaj.org/article/91bfabc34f474cfeb3a50c2a484d8f87