Zobrazeno 1 - 7
of 7
pro vyhledávání: '"Yunbing Pang"'
Publikováno v:
ASICON
Area models were proposed to estimate the implementation area in the early stage of chip design, and it is widely used in architectural exploration of advanced FPGA blocks and transistor sizing of FPGA interconnect circiuts. Models in previous works
Externí odkaz:
https://explore.openaire.eu/search/publication?articleId=doi_________::8046cc0c14ec2f90b9c5eb42936e50f6
https://doi.org/10.1109/asicon47005.2019.8983580
https://doi.org/10.1109/asicon47005.2019.8983580
Publikováno v:
ASICON
The transistor-level optimization of FPGAs faces a huge challenge due to the programmability. We don't know what kinds of end-user's circuit will be implemented on the FPGA. This means that the critical path is unknown at design time. To handle this
Externí odkaz:
https://explore.openaire.eu/search/publication?articleId=doi_________::2598899742d04e76d346b832d56f40d3
https://doi.org/10.1109/asicon47005.2019.8983550
https://doi.org/10.1109/asicon47005.2019.8983550
Publikováno v:
ASICON
A low-delay configurable register for FPGA is designed in this paper. This design is based on the basic master-slave D flip-flop, uses transmission gates on key nodes to control the register into four modes: register mode, latch mode, synchronous ove
Externí odkaz:
https://explore.openaire.eu/search/publication?articleId=doi_________::78be355b0622fb3cb73ee17f6b30e5c2
https://doi.org/10.1109/asicon47005.2019.8983553
https://doi.org/10.1109/asicon47005.2019.8983553
Publikováno v:
ACM Great Lakes Symposium on VLSI
Due to its dominance in FPGA area and delay, the interconnect circuit is traditionally designed and optimized in full customized fashion, which can be extremely time consuming. In this paper, we propose an automated transistor-level sizing optimizati
Externí odkaz:
https://explore.openaire.eu/search/publication?articleId=doi_________::6c925647d46599103ae797e3bfb7af05
https://doi.org/10.1145/3299874.3318003
https://doi.org/10.1145/3299874.3318003
Publikováno v:
FPGA
Due to its dominance in the whole chip area, power and delay, the FPGA interconnect circuits are traditionally designed by full custom design method. We present an automated transistor-level sizing optimization methodology for GRM FPGA interconnect c
Externí odkaz:
https://explore.openaire.eu/search/publication?articleId=doi_________::a22854f50db62d93318ac9134c333326
https://doi.org/10.1145/3289602.3293955
https://doi.org/10.1145/3289602.3293955
Publikováno v:
2018 14th IEEE International Conference on Solid-State and Integrated Circuit Technology (ICSICT).
Since the interconnect resources in FPGA cost more than 70% of the chip area, signal delay and power, it plays a crucial role in the implementation of high performance and lower power FPGA to improve performance and reduce power of the interconnect r
Externí odkaz:
https://explore.openaire.eu/search/publication?articleId=doi_________::b00524d82b72ef9b0deaac5b61e5c25a
https://doi.org/10.1109/icsict.2018.8564894
https://doi.org/10.1109/icsict.2018.8564894
Publikováno v:
2018 14th IEEE International Conference on Solid-State and Integrated Circuit Technology (ICSICT).
FPGA devices are becoming more widely used in various industries due to their field-programmable features. Its basic unit in configurable logic block(CLB) is the look-up table(LUT), which takes the important part in whole path delay. Most of the prev
Externí odkaz:
https://explore.openaire.eu/search/publication?articleId=doi_________::cff881ae11ba8b3f26d227ba114fb02d
https://doi.org/10.1109/icsict.2018.8564803
https://doi.org/10.1109/icsict.2018.8564803