Výsledky vyhledávání - "Yun-Yan Chung"

High On-State Current in Chemical Vapor Deposited Monolayer MoS2 nFETs With Sn Ohmic Contacts

Autor: Wen-Hao Chang, Lain-Jong Li, Ang-Sheng Chou, Shih-Yun Wang, Yun-Yan Chung, Chih-I Wu, Po-Hsun Ho, Yuan-Chun Su, Zheng-Da Huang, Yu-Chen Chang, San-Lin Liew, Chao-Ching Cheng, Fang-Yu Fu, Chen-Feng Hsu, Che-Kang Chang

Publikováno v: IEEE Electron Device Letters. 42:272-275

Proving the device performance and process feasibility is imperative for the realization of two-dimensional (2D) semiconductor electronics. In this work, we have successfully adopted Tin (Sn) as the Ohmic contact metal to monolayer molybdenum disulfi

Externí odkaz: https://explore.openaire.eu/search/publication?articleId=doi_________::f9e3d8d087258cd32532d4b70336b29f
https://doi.org/10.1109/led.2020.3048371

Zobrazit plný text záznamu

High-Accuracy Deep Neural Networks Using a Contralateral-Gated Analog Synapse Composed of Ultrathin MoS₂ nFET and Nonvolatile Charge-Trap Memory

Autor: Zhihao Yu, Lin-Yun Huang, Lain-Jong Li, Chao-Ching Cheng, Chao-Hsin Chien, Yun-Yan Chung, Wei-Chen Chueh, Shin-Yuan Wang, Li-Cheng Teng, Yu-Che Chou, Terry Yi-Tse Hung, Wen-Ho Chang, Wan-Hsuan Chung

Publikováno v: IEEE Electron Device Letters. 41:1649-1652

The development of high-accuracy analog synapse deep neural networks entails devising novel materials and innovative memory structures. We demonstrated an analog synapse with contralateral gates based on a two-dimensional (2D) field-effect transistor

Externí odkaz: https://explore.openaire.eu/search/publication?articleId=doi_________::b70c2daf3d7702ca6d14ecfde9d0f386
https://doi.org/10.1109/led.2020.3026931

Zobrazit plný text záznamu

Demonstration of 40-nm Channel Length Top-Gate p-MOSFET of WS2 Channel Directly Grown on SiO$_{{x}}$ /Si Substrates Using Area-Selective CVD Technology

Autor: Chao-Ting Lin, Kai-Shin Li, Wen-Bin Jian, Chao-Ching Cheng, Sheng-Kai Su, Chao-Hsin Chien, Jyun-Hong Chen, Lain-Jong Li, Tung-Yen Lai, Chen Tzu-Chiang, Ming-Yang Li, Chiang Hung-Li, Jia-Min Shieh, Chi-Feng Li, H.-S. Philip Wong, Kuan-Cheng Lu, Yun-Yan Chung

Publikováno v: IEEE Transactions on Electron Devices. 66:5381-5386

For high-volume manufacturing of 2-D transistors, area-selective chemical reaction deposition (CVD) growth is able to provide good-quality 2-D layers and may be more effective than exfoliation from bulk crystals or wet/dry transfer of large-area as-g

Externí odkaz: https://explore.openaire.eu/search/publication?articleId=doi_________::ff63a9035ccdd2bce1f895c45625cab8
https://doi.org/10.1109/ted.2019.2946101

Zobrazit plný text záznamu

Pinning-Free Edge Contact Monolayer MoS2 FET

Autor: Feng-Shew Huang, Chao-Hsin Chien, Shih-Yun Wang, Ang-Sheng Chou, Lain-Jong Li, Yun-Yan Chung, Ming-Yang Li, Chao-Ching Cheng, Wen-Hao Chang, Tac Chen, H.-S. Philip Wong, Jin Cai, Terry Y.T. Hung, Chih-Piao Chuu

Publikováno v: 2020 IEEE International Electron Devices Meeting (IEDM).

One-dimensional contact (so-called edge contact) to monolayer 2D materials has been proposed for ultimate transistor scaling but reported on-state currents are much lower than those from top contact devices. Experiments in this work reveal that the f

Externí odkaz: https://explore.openaire.eu/search/publication?articleId=doi_________::b605ff88bcd17cf4eda0318f8e8e5fc2
https://doi.org/10.1109/iedm13553.2020.9372028

Zobrazit plný text záznamu

Switchable NAND and NOR Logic Computing in Single Triple-Gate Monolayer MoS2 n-FET

Autor: Chao-Hsin Chien, Wei-Chen Chueh, Chen-Han Chou, Shih-Yun Wang, Terry Y.T. Hung, Yun-Yan Chung, Shin-Yuan Wang, Wen-Hao Chang, Lain-Jong Li, Bo-Kai Kang, Chao-Ching Cheng

Publikováno v: 2020 IEEE International Electron Devices Meeting (IEDM).

We propose a novel triple-gated single transistor comprising monolayer MoS 2 channel to accomplish basic logic-gate functions. The NAND and NOR computing are compatible in the same MoS 2 n-FET and switchable easily through top-gate bias setting (V LO

Externí odkaz: https://explore.openaire.eu/search/publication?articleId=doi_________::477fa5fbbbf4808cf5d122e67e1d9eab
https://doi.org/10.1109/iedm13553.2020.9372072

Zobrazit plný text záznamu

First demonstration of 40-nm channel length top-gate WS2 pFET using channel area-selective CVD growth directly on SiOx/Si substrate

Autor: Chen Tzu-Chiang, Jyun-Hong Chen, Chao-Ching Cheng, Tung-Yen Lai, Chiang Hung-Li, Yun-Yan Chung, Sheng-Kai Su, Chao-Ting Lin, Jia-Min Shieh, Lain-Jong Li, Chi-Feng Li, Chao-Hsin Chien, Kai-Shin Li, Uing-Yang Li, H.-S. Philip Wong

Publikováno v: 2019 Symposium on VLSI Technology.

Area-selective channel material growth for 2D transistors is more desirable for volume manufacturing than exfoliation or wet/dry transfer after large area growth. We demonstrate the first top-gate WS 2 p-channel field-effect transistors (p-FETs) fabr

Externí odkaz: https://explore.openaire.eu/search/publication?articleId=doi_________::e1c7d0057982eb7957e0c27afceae055
https://doi.org/10.23919/vlsit.2019.8776498

Zobrazit plný text záznamu

A Comparative Study of NBTI and RTN Amplitude Distributions in High- $\kappa$ Gate Dielectric pMOSFETs

Autor: Chih-Yuan Lu, K. F. Yu, Yun-Yan Chung, J.P. Chiu, Tahui Wang, Min-Cheng Chen

Publikováno v: IEEE Electron Device Letters. 33:176-178

Random telegraph noise (RTN) and negative bias temperature (NBT) stress-induced threshold voltage (Vt) fluctuations in high-κ gate dielectric and metal-gate pMOSFETs are investigated. We measured RTN amplitude distributions before and after NBT stre

Externí odkaz: https://explore.openaire.eu/search/publication?articleId=doi_________::18f240734f74a1e2b8ab844eb64330dc
https://doi.org/10.1109/led.2011.2176912

Zobrazit plný text záznamu

Vyhledávací nástroje:

Upřesnit hledání