Zobrazeno 1 - 9
of 9
pro vyhledávání: '"Yun-Chih Kuo"'
Autor:
Yun-Chih Kuo, 郭玧質
106
The benefits of using FPGAs, such as the high flexibility to reconfigure functionality, the short turnaround time to market, and the natural fit for high-end control applications, have attracted higher attention from circuit designers in rec
The benefits of using FPGAs, such as the high flexibility to reconfigure functionality, the short turnaround time to market, and the natural fit for high-end control applications, have attracted higher attention from circuit designers in rec
Externí odkaz:
http://ndltd.ncl.edu.tw/handle/sudhq2
Autor:
Yun-Chih Kuo, 郭芸之
93
Marching toward 21st century the era called “the kownledge economy”, knowledge has already solemnly become any organization to depend on the key factor of continuing and seeking development. Grasp and managerial knowledge effectively, it
Marching toward 21st century the era called “the kownledge economy”, knowledge has already solemnly become any organization to depend on the key factor of continuing and seeking development. Grasp and managerial knowledge effectively, it
Externí odkaz:
http://ndltd.ncl.edu.tw/handle/01431922551211256384
Autor:
Yeu-Haw Yeh, Simon Yi-Hung Chen, Hung-Ming Chen, Deng-Yao Tu, Guan-Qi Fang, Yun-Chih Kuo, Po-Yang Chen
Publikováno v:
Proceedings of the 28th Asia and South Pacific Design Automation Conference.
Externí odkaz:
https://explore.openaire.eu/search/publication?articleId=doi_________::1ad46fbb12948aa81974eb2864339f2b
https://doi.org/10.1145/3566097.3567902
https://doi.org/10.1145/3566097.3567902
Autor:
Jianli Chen, Zhifeng Lin, Yun-Chih Kuo, Chau-Chin Huang, Yao-Wen Chang, Shih-Chun Chen, Chun-Han Chiang, Sy-Yen Kuo
Publikováno v:
ICCAD
A modern FPGA often contains an ASIC-like clocking architecture which is crucial to achieve better skew and performance. Existing conventional FPGA placement algorithms seldom consider clocking resources, and thus may lead to clock routing failures.
Externí odkaz:
https://explore.openaire.eu/search/publication?articleId=doi_________::e4595d785ab5fe7eb437e460f0e908db
https://doi.org/10.1109/tcad.2020.2968892
https://doi.org/10.1109/tcad.2020.2968892
Autor:
Yeu-Haw Yeh, Simon Yi-Hung Chen, Hung-Ming Chen, Deng-Yao Tu, Guan-Qi Fang, Yun-Chih Kuo, Po-Yang Chen
Publikováno v:
2022 International Symposium on VLSI Design, Automation and Test (VLSI-DAT).
Externí odkaz:
https://explore.openaire.eu/search/publication?articleId=doi_________::971ffed498103ac4937bf233f61d68f7
https://doi.org/10.1109/vlsi-dat54769.2022.9768081
https://doi.org/10.1109/vlsi-dat54769.2022.9768081
Autor:
Hao-Yu Chi, Simon Yi-Hung Chen, Hung-Ming Chen, Chien-Nan Liu, Yun-Chih Kuo, Ya-Hsin Chang, Kuan-Hsien Ho
Publikováno v:
2022 Design, Automation & Test in Europe Conference & Exhibition (DATE).
Externí odkaz:
https://explore.openaire.eu/search/publication?articleId=doi_________::ef27da302d27ce638a1c481e2ae363a4
https://doi.org/10.23919/date54114.2022.9774733
https://doi.org/10.23919/date54114.2022.9774733
Publikováno v:
DATE
In modern package design, the bumps often place irregularly due to the macros varied in sizes and positions. This will make pre-assignment routing more difficult, even with massive design efforts. This work presents a 2-stage routing method which can
Externí odkaz:
https://explore.openaire.eu/search/publication?articleId=doi_________::f1c5b8d0c2e8b75d80a02a43a3362655
https://doi.org/10.23919/date48585.2020.9116421
https://doi.org/10.23919/date48585.2020.9116421
Publikováno v:
DAC
As interconnects dominate circuit performance in modern chip designs, placement becomes an essential stage in optimizing timing. Recent timing-driven placement (TDP) techniques focus mainly on optimizing late slack rather than early slack. This paper
Externí odkaz:
https://explore.openaire.eu/search/publication?articleId=doi_________::297f3e124c831415dbf8b972cb26b36c
https://doi.org/10.1145/2897937.2898105
https://doi.org/10.1145/2897937.2898105
Publikováno v:
DAC: Annual ACM/IEEE Design Automation Conference; Jun2016, p475-480, 6p