Zobrazeno 1 - 10
of 51
pro vyhledávání: '"Yuefei Ge"'
Autor:
King C. Yen, Aparna Ramachandran, Timothy P. Johnson, Yongning Sheng, Jason M. Hart, Daisy Jian, Rakesh Mehta, Yuefei Ge, Dawei Huang, Lance Kwong, Hoyeol Cho, Zuxu Qin, Changku Hwang, Jinuk Luke Shin, Umesh Gajanan Nawathe, Robert P. Masleid, Venkat Krishnaswamy, Georgios Konstadinidis, Hari Sathianathan, Gregory Gruber, Sebastian Turullols
Publikováno v:
ISSCC
The 3.6 GHz SPARC T5 processor is Oracle's next generation CMT SoC processor implemented in TSMC's 28 nm process with 1.5 billion transistors. Significant performance improvements were made by doubling the previous generations number of cores to 16 a
Externí odkaz:
https://explore.openaire.eu/search/publication?articleId=doi_________::d9a65bf3aeb8482508a1512e9ba2b864
https://doi.org/10.1109/jssc.2013.2284648
https://doi.org/10.1109/jssc.2013.2284648
Publikováno v:
Enterprise Innovation. Oct2007, Vol. 3 Issue 5, p10-10. 1/4p.
Autor:
I. Parulkar, Peter F. Lai, Georgios Konstadinidis, Yuefei Ge, S. Parampalli, Marc Tremblay, Ilyas Elkin, Mamun Rashid, Y. Otaguro, Shailender Chaudhry, Leonard D. Rarick, Rambabu Pyapali, Y. Orginos, S. Gundala, M. Steigerwald
Publikováno v:
IEEE Journal of Solid-State Circuits. 44:7-17
This third-generation Chip-Multithreading (CMT) SPARC processor consists of 16 cores with shared memory architecture and supports a total of 32 main threads plus 32 scout threads. It is targeted for high-performance servers, and is optimized for both
Externí odkaz:
https://explore.openaire.eu/search/publication?articleId=doi_________::a4795759c9064aced8f04104bb89a687
https://doi.org/10.1109/jssc.2008.2007144
https://doi.org/10.1109/jssc.2008.2007144
Autor:
Choon Ping Chng, A.A. Martin, Baoqing Huang, Sourav Ghosh, Xin Liu, S. Zambere, B. Sur, V. Adler, Tan Canh Hoang, N.G. Malur, Marc Tremblay, A. Liebermensch, Suman Kant, Cong Khieu, S. Kumar, F. Chiu, Sung-Hun Oh, Jin Zong, I. Orginos, D. Vo, Yuefei Ge, Hiep Ngo, Allan Tzeng, L. Shih, A. Kowalczyk, Lan Lee, W.J. de Lange, Y.S. Kao, C. Amir
Publikováno v:
IEEE Journal of Solid-State Circuits. 36:1609-1616
The first implementation of MAJC architecture achieves high performance by using very long instruction word (VLIW), single instruction multiple data (SIMD), and chip multiprocessing. The chip integrates two processors, a memory controller, two high-s
Externí odkaz:
https://explore.openaire.eu/search/publication?articleId=doi_________::b8f44a1fd32847413217e2c63d26f406
https://doi.org/10.1109/4.962280
https://doi.org/10.1109/4.962280
Autor:
J. Hart, S. Butler, null Hoyeol Cho, null Yuefei Ge, G. Gruber, null Dawei Huang, null Changku Hwang, D. Jian, T. Johnson, G. Konstadinidis, L. Kwong, R. Masleid, U. Nawathe, A. Ramachandran, null Yongning Sheng, J. L. Shin, S. Turullois, null Zuxu Qin, null King Yen
Publikováno v:
2013 IEEE International Solid-State Circuits Conference Digest of Technical Papers.
Externí odkaz:
https://explore.openaire.eu/search/publication?articleId=doi_________::d740206905b739c2a7fb6049394c3258
https://doi.org/10.1109/isscc.2013.6487631
https://doi.org/10.1109/isscc.2013.6487631
Autor:
Konstadinidis, G., Rashid, M., Lai, P.F., Otaguro, Y., Orginos, Y., Parampalli, S., Steigerwald, M., Gundala, S., Pyapali, R., Rarick, L., Elkin, I., Yuefei Ge, Parulkar, I.
Publikováno v:
2008 IEEE International Solid-State Circuits Conference - Digest of Technical Papers; 2008, p84-597, 514p
Autor:
Ilyas Elkin, Mamun Rashid, I. Parulkar, M. Steigerwald, Yuefei Ge, S. Gundala, Peter F. Lai, Y. Otaguro, Leonard D. Rarick, Rambabu Pyapali, Y. Orginos, Georgios Konstadinidis, S. Parampalli
Publikováno v:
ISSCC
This third-generation chip-multithreading (CMT) SPARC processor is targeted for high-performance servers, and is optimized for both single- and multi-threaded applications. The architecture highlights are provided in [M. Tremblay and S. Chaudhry, 200
Externí odkaz:
https://explore.openaire.eu/search/publication?articleId=doi_________::c6b76b36751fa45dd047559b8fdbc3f1
https://doi.org/10.1109/isscc.2008.4523068
https://doi.org/10.1109/isscc.2008.4523068
Autor:
C. Amir, D. Vo, D. Pini, A. Kowalczyk, Xin Liu, Sung-Hun Oh, Baoqing Huang, V. Adler, S. Kumar, Sourav Ghosh, Lan Lee, B. Sur, Allan Tzeng, N.G. Malur, Yuefei Ge, Chung Lau, W.J. de Lange, S. Zambare, Y.S. Kao, Cong Khieu, Jin Zong, F. Chiu, A. Liebermensch, Tan Hoang, S. Dubler, I. Orginos, Choon Chug, L. Shih, R. Hu, Suman Kant, Hiep Ngo
Publikováno v:
2001 IEEE International Solid-State Circuits Conference. Digest of Technical Papers. ISSCC (Cat. No.01CH37177).
The MAJC 5200 is a dual 32b microprocessor system-on-a-chip, utilizing 0.22 /spl mu/m CMOS with all-Cu interconnect. Two CPUs, delivering GGFLOPS and 13GOPS at 500 MHz, are tightly coupled through a shared, coherent, 4-way set associative 16 KB data
Externí odkaz:
https://explore.openaire.eu/search/publication?articleId=doi_________::4cc9093764d1aa84e731202d34375288
https://doi.org/10.1109/isscc.2001.912619
https://doi.org/10.1109/isscc.2001.912619
Autor:
Kowalczyk, A., Adler, V., Amir, C., Chiu, F., Choon Ping Chng, De Lange, W.J., Yuefei Ge, Ghosh, S., Tan Canh Hoang, Baoqing Huang, Kant, S., Kao, Y.S., Cong Khieu, Kumar, S., Lan Lee, Liebermensch, A., Xin Liu, Malur, N.G., Martin, A.A., Ngo, H.
Publikováno v:
IEEE Journal of Solid-State Circuits; Nov2001, Vol. 36 Issue 11, p1609-1616, 8p