Zobrazeno 1 - 10
of 11
pro vyhledávání: '"Yue-Gie Liaw"'
Autor:
Deshi Li, Chii-Wen Chen, Wen-Shiang Liao, Haoshuang Gu, Mu-Chun Wang, Xuecheng Zou, Yue-Gie Liaw
Publikováno v:
Semiconductors. 51:1650-1655
The length of Source/Drain (S/D) extension (LSDE) of nano-node p-channel FinFETs (pFinFETs) on SOI wafer influencing the device performance is exposed, especially in drive current and gate/S/D leakage. In observation, the longer LSDEpFinFET provides
Autor:
Cheng-Li Lin, Mu-Chun Wang, Haoshuang Gu, Bin Zhou, Deshi Li, Xuecheng Zou, Wen-Shiang Liao, Yue-Gie Liaw
Publikováno v:
Solid-State Electronics. 126:46-50
Three dimensional (3-D) FinFET devices with an ultra-high Si-fin aspect ratio (Height/Width = 82.9 nm/8.6 nm) have been developed after integrating a 14 A nitrided gate oxide upon the silicon on insulator (SOI) wafers through an advanced CMOS logic p
Publikováno v:
Modern Physics Letters B. 32:1850157
Nano-node tri-gate FinFET devices have been developed after integrating a 14 Å nitrided gate oxide upon the silicon-on-insulator (SOI) wafers established on an advanced CMOS logic platform. These vertical double gate (FinFET) devices with ultra-thin
Autor:
Xuecheng Zou, Haoshuang Gu, Deshi Li, Chii-Wen Chen, Mu-Chun Wang, Wen-Shiang Liao, Yue-Gie Liaw
Publikováno v:
Физика и техника полупроводников. 51:1706
The length of Source/Drain (S/D) extension (LSDE) of nano-node p-channel FinFETs (pFinFETs) on SOI wafer influencing the device performance is exposed, especially in drive current and gate/S/D leakage. In observation, the longer LSDE pFinFET provides
Autor:
Lee Chung, Tommy Shih, Mao-Chyuan Tang, Chee-Wee Liu, Huan-Chiu Tsen, Yue-Gie Liaw, Sheng-Yi Huang, Wen-Shiang Liao, Kun-Ming Chen
Publikováno v:
Japanese Journal of Applied Physics. 47:3127-3129
It is demonstrated that the appropriate external mechanical stress applied by the conventional IC chip's package straining can enhance device and circuit performance. A drain current enhancement of 4.9% at saturation is observed for 90-nm-node n-chan
Autor:
Kun-Ming Chen, Chee-Wee Liu, Sheng-Yi Huang, Mao-Chyuan Tang, Wen-Shiang Liao, Yue-Gie Liaw, Cheng-Yi Peng
Publikováno v:
IEEE Electron Device Letters. 29:86-88
In this letter, the SiGe-channel PMOS transistors integrated with a highly compressive contact-etching stop-layer (CESL) interlayer-dielectric-SiNx stressing layer have been successfully fabricated. The performance improvements of devices with a gate
Autor:
Tung-Hung Chen, Hsin-Hung Lin, Mao-Chyuan Tang, Yu-Huan Liu, Sheng-Yi Huang, Yue-Gie Liaw, Tommy Shih, Kun-Ming Chen, Cheng-Han Wu, Wen-Shiang Liao
Publikováno v:
Advances in Resist Materials and Processing Technology XXV.
As the IC product scribe line of logic 90nm (L90) technology shrinks from 80µm to 62μm, the wafer quality (W.Q.), will become weak and less distinguishable during the subsequent ASML scanner stepper's photo mask aligning. Many wafers having photo m
Autor:
Tung-Hung Chen, Lee Chung, Sheng-Yi Huang, Tommy Shih, Kun-Ming Chen, Mao-Chyuan Tang, Yue-Gie Liaw, Cheng-Han Wu, Wen-Shiang Liao, Huan-Chiu Tsen
Publikováno v:
SPIE Proceedings.
A vertical double gate MOSFET (FinFET) device with an ultra-small poly-Si gate of 30nm and promising device performances has been successfully developed after integrating a 14a nitrided gate oxide on silicon-on-insulator (SOI) wafers. First, a 500a-t
Autor:
Hao-Hao Wang, Hsin-Chia Yang, Haoshuang Gu, Szu-Hung Chen, Wen-Shiang Liao, Mu-Chun Wang, Yue-Gie Liaw, Shea-Jue Wang
Publikováno v:
Nanoscale Research Letters
A three-dimensional (3D) fin-shaped field-effect transistor structure based on III-V metal-oxide-semiconductor field-effect transistor (MOSFET) fabrication has been demonstrated using a submicron GaAs fin as the high-mobility channel. The fin-shaped
Autor:
Haoshuang Gu, Kun-Ming Chen, Mu-Chun Wang, Yue-Gie Liaw, Cong Ye, Hao Wang, Di Zhou, Szu-Hung Chen, Yongming Hu, Wen-Shiang Liao, Wenfeng Wang
Publikováno v:
Applied Physics Letters. 99:173505
A high-aspect-ratio 3D multi-gate n-channel fin-shaped field effect transistor (FinFET) has been integrated with a stressor of a highly tensile nitride film as the initial inter layer dielectric capping layer upon a (110)-orientated silicon-on-insula