Zobrazeno 1 - 10
of 18
pro vyhledávání: '"Yue Ying Ong"'
Publikováno v:
Journal of Chemical Education. 97:87-96
Chemical waste should be reduced to minimize environmental pollution, and it is important that the amount of waste is minimized in chemistry teaching laboratories to reduce the negative impact on environment as well as the disposal costs of universit
Autor:
Pinjala Damaruganath, M Ravi, John H. Lau, Ebin Liao, Vempati Srinivasa Rao, Nagarajan Ranganathan, Hong Yu Li, Yen Yi Germaine Hoe, Jiangyan Sun, Xiaowu Zhang, Eva Wai, Tai Chong Chai, C. J. Vath, C. S. Selvanayagam, Y Tsutsumi, Yue Ying Ong, Shiguo Liu, Kripesh Vaidyanathan
Publikováno v:
IEEE Transactions on Components, Packaging and Manufacturing Technology. 1:660-672
The continuous push for smaller bump pitch interconnection in line with smaller Cu/low-k technology nodes demands the substrate technology to support finer interconnection. However, the conventional organic buildup substrate is facing a bottleneck in
Autor:
Xuefen Ong, Seung Uk Yoon, Juan Boon Tan, John H. Lau, Yue Ying Ong, Lim Yeow Kheng, Kai Chong Chan, David Yeo, Dong Kyun Sohn, Yanfeng Zhang, Xiaowu Zhang, J. Ong, Soon Wee Ho, Kripesh Vaidyanathan, V. N. Sekhar
Publikováno v:
IEEE Transactions on Components, Packaging and Manufacturing Technology. 1:279-290
This paper presents a systematic underfill selection and characterization methods for 21 ×21 mm2 Cu/low-K flip chip packages (65 nm technology) with 150 μm bump pitch. This paper has also correlated the underfill characterization methods with the r
Autor:
Xiaowu Zhang, John H. Lau, David Yeo, Xuefen Ong, Samuel Lim Yak Long, Vempati Srinivasa Rao, Yoon Uk Seung, V. N. Sekhar, Soon Wee Ho, Kripesh Vaidyanathan, Jimmy Ong, Juan Boon Tan, Ming Chinq Jong, Leong Ching Wai, Yue Ying Ong, Kai Chong Chan, Dong Kyun Sohn, Zhang Yanfeng, Y.K. Lim, Vincent Lee Wen Sheng
Publikováno v:
Microelectronics Reliability. 50:986-994
This paper reports the design, assembly and reliability assessment of 21 × 21 mm 2 Cu/low- k flip chip (65 nm node) with 150 μm bump pitch and high bump density. To reduce the stress from the solder bump pad to low- k layers, Metal Redistribution L
Autor:
Dim-Lee Kwong, Venky Sundaram, John H. Lau, Xiaowu Zhang, Yue Ying Ong, Soon Wee Ho, Chee Houe Khong, R.R. Tummula, Aditya Kumar, V. Kripesh, Qing Xin Zhang, Georg Meyer-Berg
Publikováno v:
Sensors and Actuators A: Physical. 156:2-7
Because of 3D integration, thickness of Silicon wafer is thinner and thinner. For thin silicon ICs, challenges in wafer thinning, handling and assembly process increase. The piezoresistive stress sensors studied in this paper are for experimental pur
Autor:
Yue Ying Ong, Zhong Chen, Juan Boon Tan, Leong Ching Wai, Kai Chong Chan, Soon Wee Ho, Dong Kyun Sohn, David Yeo, Xuefen Ong, Liang Choo Hsia, Y.K. Lim, Kripesh Vaidyanathan
Publikováno v:
Microelectronics Reliability. 49:150-162
A systematic underfill selection approach has been presented to characterize and identify suitable underfill encapsulants for large size flip chip ball grid array (FCBGA) packages. In the selection scheme, a total of six evaluation factors such as fr
Publikováno v:
J. Mater. Chem.. 17:1002-1006
Thermolysis of {(n-C4H9)4N[MnIICrIII(C2O4)3]}n, 1 at 500 °C for 10 h gives spinel Mn1.5Cr1.5O4 which was characterized by powder XRD, SEM, FTIR and elemental analysis. The thermal conversion occurs by an internal redox process at ca. 400 °C in one
Autor:
Vempati Srinivasa Rao, Xiaowu Zhang, Eipa Myo, Leong Ching Wai, Pinjala Damaruganath, Tai Chong Chai, Daquan Yu, Yue Ying Ong, Meei Leng Thew, Nandar Su, Ming Chinq Jong
Publikováno v:
2009 11th Electronics Packaging Technology Conference.
This paper presents the assembly optimization and charcterierization of Through-Silicon Vias (TSV) interposer technology for two 8 × 10mm2 micro-bumped chips. The two micro-bumped chips represent different functional dies in a System-in-package (SiP
Autor:
Daquan Yu, Meei Ling Thew, Leong Ching Wai, Yue Ying Ong, John H. Lau, Vempati Srinivasa Rao, Tai Chong Chai
Publikováno v:
2009 59th Electronic Components and Technology Conference.
Electromigration (EM) of micro bumps of 50 µm pitch was studied using four-point Kelvin structure. Two kinds of bumps, i. e., SnAg solder bump and Cu post with SnAg solder were tested. These bumps with thick Cu under bump metallization (UBM) were bo
Autor:
John H. Lau, V. Kripesh, Yue Ying Ong, John Doricko, Jiangyan Sun, Nagarajan Ranganathan, Damaruganath Pinjala, Shiguo Liu, Xiaowu Zhang, Gongyue Tang, Tai Chong Chai, Eva Wai, C. J. Vath, Ebin Liao, Srinivasa Rao Vempati, C. S. Selvanayagam, Kalyan Biswas, Hongyu Li
Publikováno v:
2009 59th Electronic Components and Technology Conference.
Because of Moore's (scaling/integration) law, the Cu/low-k silicon chip is getting bigger, the pin-out is getting higher, and the pitch is getting finer. Thus, the conventional organic buildup substrates cannot support these kinds of silicon chips an