Zobrazeno 1 - 10
of 42
pro vyhledávání: '"Yuan-Chang Lee"'
Autor:
Yuan-Chang Lee, 李源彰
94
A 3D Camera Capture System architecture based on a low cost and high performance DSP is proposed in this paper. The host processor can read out dual frame images simultaneously through USB 2.0 interface. The camera parameters are calibrated t
A 3D Camera Capture System architecture based on a low cost and high performance DSP is proposed in this paper. The host processor can read out dual frame images simultaneously through USB 2.0 interface. The camera parameters are calibrated t
Externí odkaz:
http://ndltd.ncl.edu.tw/handle/5pr2p6
Autor:
Sheng-Chieh Lin, Geng-Hao Bai, Pei-Chun Lin, Chung-Yung Chen, Yi-Hsiang Hsu, Yuan-Chang Lee, Shih-Yen Chen
Publikováno v:
International Journal of Molecular Sciences. 24:9093
Human noroviruses (HuNoV) are major causes of acute gastroenteritis around the world. The high mutation rate and recombination potential of noroviruses are significant challenges in studying the genetic diversity and evolution pattern of novel strain
Externí odkaz:
https://explore.openaire.eu/search/publication?articleId=doi_________::b93122dffe3c67efb7cf22bcdd4e60d5
https://doi.org/10.3390/ijms24109093
https://doi.org/10.3390/ijms24109093
Autor:
Lin Ang-Ying, Xiao Liu, Yu-Min Lin, Tao-Chih Chang, Kuan-Neng Chen, Jay Su, Huan-Chun Fu, Shu-Man Lee, Shin-Yi Huang, Dongshun Bai, Wen-Wei Shen, Baron Huang, Tzu-Ying Kuo, Hsiang-Hung Chang, Alvin Lee, Yuan-Chang Lee
Publikováno v:
2017 IEEE 67th Electronic Components and Technology Conference (ECTC).
Fan-out wafer-level-packaging (FO-WLP) technology is developed with the advantages of smaller package size, higher Input/Output (I/O) counts, lower cost, and better performance. In this study, the FO-WLP technology is applied to TSV-less inter-connec
Externí odkaz:
https://explore.openaire.eu/search/publication?articleId=doi_________::cf2ca606ae3a8e598e840774cd4f23cb
https://doi.org/10.1109/ectc.2017.262
https://doi.org/10.1109/ectc.2017.262
Autor:
Shang-Chun Chen, Tzu-Chien Hsu, Jen-Chun Wang, Jui-Chin Chen, Chung-Chih Wang, Yu-Chen Hsin, Yiu-Hsiang Chang, Tsuen-Sung Chen, Hsiang-Hung Chang, Chiung-Yu Lo, Po-Chih Chang, Yuan-Chang Lee, Chih-Lin Wang, Chao-Kai Hsu, Su-Hsin Lin
Publikováno v:
2016 11th International Microsystems, Packaging, Assembly and Circuits Technology Conference (IMPACT).
In this paper, we show the process and integration results of small TSVs integrated by 300mm 3DIC BTSV process. The TSV size is from 2um to 3um (in diameter) with aspect ratio of 10. The achievements of this work are: 1) successful demonstration of 2
Externí odkaz:
https://explore.openaire.eu/search/publication?articleId=doi_________::72b2bb01616968cd387305033cb62095
https://doi.org/10.1109/impact.2016.7800041
https://doi.org/10.1109/impact.2016.7800041
Autor:
Kuo-Chyuan Chen, Hsiang-Hung Chang, Yuan-Chang Lee, Ching-Kuan Lee, Yung Jean Rachel Lu, Jen-Chun Wang, Chia-Wen Fan, Wen-Wei Shen, Huan-Chun Fu, Chau-Jie Zhan
Publikováno v:
2016 11th International Microsystems, Packaging, Assembly and Circuits Technology Conference (IMPACT).
In this paper, we investigate reliability testing for a glass interposer. The test vehicle is an assembled glass interposer with a chip, a BT substrate. The structure of a glass interposer with two redistribution layers (RDLs) on the front-side and o
Externí odkaz:
https://explore.openaire.eu/search/publication?articleId=doi_________::13274814741472ba8d69ee6216ec234c
https://doi.org/10.1109/impact.2016.7800011
https://doi.org/10.1109/impact.2016.7800011
Autor:
Yu-Min Lin, Chia-Wen Fan, Chau-Jie Zhan, Wen-Wei Shen, Huan-Chun Fu, Su-Ching Chung, Su-Mei Chen, Chia-Wen Chiang, Jen-Chun Wang, Wei-Chung Lo, Hsiang-Hung Chang, Yuan-Chang Lee, Ching-Kuan Lee, Yung Jean Lu
Publikováno v:
2016 International Conference on Electronics Packaging (ICEP).
In this paper, we investigated the reliability test for Glass interposer. The test vehicle is assembled glass interposer with chip, BT substrate, and PCB. The structure of a glass interposer with two RDL on the front-side and one RDL on the backside
Externí odkaz:
https://explore.openaire.eu/search/publication?articleId=doi_________::898d8169fccb5afa005ad60b72aab4ca
https://doi.org/10.1109/icep.2016.7486780
https://doi.org/10.1109/icep.2016.7486780
Autor:
Su-Mei Chen, Yu-Min Lin, Huan-Chun Fu, Yung Jean Lu, Chia-Wen Fan, Jen-Chun Wang, C. W. Chiang, Wei-Chung Lo, Yuan-Chang Lee, Ching-Kuan Lee, Chau-Jie Zhan, Wen-Wei Shen, Su-Ching Chung
Publikováno v:
2015 10th International Microsystems, Packaging, Assembly and Circuits Technology Conference (IMPACT).
In this paper, we investigated the assembly characterization for reliability test. The structure of a glass interposer with two RDL on the front-side and one RDL on the backside had been evaluated and developed. Key technologies, including via fabric
Externí odkaz:
https://explore.openaire.eu/search/publication?articleId=doi_________::6283e5d1c3239395f0435922865a4741
https://doi.org/10.1109/impact.2015.7365220
https://doi.org/10.1109/impact.2015.7365220
Autor:
Huan-Chun Fu, Ming-Chieh Chou, Yu-Chih Chen, Hsiang-Hung Chang, Yuan-Chang Lee, Li-Cheng Shen, Wun-Yan Chen, Shu-Ming Chang, Wei-Chung Lo
Publikováno v:
Circuit World. 32:8-15
Purpose – To characterise the optical performance of organic multi‐mode optical waveguides integrated with printed circuit board (PCB) and to demonstrate the feasibility of 2.5 and 10 Gbps optical interconnection in board‐level, respectively.De
Externí odkaz:
https://explore.openaire.eu/search/publication?articleId=doi_________::c07b8726cfb9d274220f50b692ce907b
https://doi.org/10.1108/03056120610616508
https://doi.org/10.1108/03056120610616508
Autor:
John H. Lau, Chau-Jie Zhan, Chun-Hsien Chien, Ming-Ji Dai, Ra-Min Tain, Ming-Jer Kao, Yu-Mei Cheng, Pai-Cheng Chang, W. L. Tsai, Sheng-Tsai Wu, Yu-Lin Chao, Ren-Shin Cheng, Heng-Chieh Chien, Li-Ling Liao, Zhi-Cheng Hsiao, Yuan-Chang Lee, Ching-Kuan Lee, Yu-Wei Huang, Wei-Chung Lo, Huan-Chun Fu
Publikováno v:
2014 IEEE 64th Electronic Components and Technology Conference (ECTC).
In this investigation, a SiP (system-in-package) which consists of a very low-cost interposer with through-silicon holes (TSHs) and with chips on its top- and bottom-side (a real 3D IC integration) is studied. Emphasis is placed on the fabrication of
Externí odkaz:
https://explore.openaire.eu/search/publication?articleId=doi_________::db29d6450e946c0c6833ece0a43ee5f9
https://doi.org/10.1109/ectc.2014.6897301
https://doi.org/10.1109/ectc.2014.6897301
Autor:
Jen-Chun Wang, Pei-Jer Tzeng, Cheng-Ta Ko, Chau-Jie Zhan, Ting-Sheng Chen, S. M. Lee, C. H. Lee, Ming-Jer Kao, C. H. Chien, Yu-Wei Huang, Wei-Chung Lo, Hsiang-Hung Chang, Yuan-Chang Lee, Zhi-Cheng Hsiao
Publikováno v:
2014 International Conference on Electronics Packaging (ICEP).
In this research, a new structure and process integration for backside illuminated CMOS image sensor by using thin wafer handling technology is proposed. First of all, the wafer of a 3 Mega pixel CMOS image sensor is temporary bonded to a silicon car
Externí odkaz:
https://explore.openaire.eu/search/publication?articleId=doi_________::321f28c7e98b54cf078ea635b95cddd4
https://doi.org/10.1109/icep.2014.6826657
https://doi.org/10.1109/icep.2014.6826657