Zobrazeno 1 - 10
of 19
pro vyhledávání: '"Yu-Hwan Ro"'
Autor:
Bengseng Phuah, Hyun-Sung Shin, Jinin So, Shin-haeng Kang, Kyomin Sohn, Wang David T, Kwang-Il Park, Hyeon-Su Kim, Jihyun Choi, Joon-Ho Song, Jeonghyeon Cho, Jin-Hyun Kim, Yu-Hwan Ro, Woong-jae Song, Sukhan Lee, Seung-Won Lee, Young-Soo Sohn, Yeongon Cho, Jang-Seok Choi, Nam Sung Kim
Publikováno v:
HCS
Using PIM to overcome memory bottleneck • Although various bandwidth increase methods have been proposed, it is physically impossible to achieve a breakthrough increase. - Limited by # of PCB wires, # of CPU ball, and thermal constraints • PIM ha
Autor:
Jae-Hoon Lee, Soo-Young Kim, O Seongil, Kyomin Sohn, Myeong Jun Song, Yu-Hwan Ro, Sukhan Lee, Hyoung-Min Kim, Wang David T, Jongyoon Choi, Je Min Ryu, Eun-Bong Kim, SooYoung Kim, Nam Sung Kim, Jae-Youn Youn, Daeho Kim, Sang-Hyuk Kwon, Jin Kim, Jin Guk Kim, Jong-Pil Son, Bengseng Phuah, Hyun-Sung Shin, Hae-Suk Lee, Shin-haeng Kang, Young-Cheon Kwon, Seung-Woo Seo, Young-min Cho, Hak-soo Yu, Joon-Ho Song, Ahn Choi
Publikováno v:
ISSCC
In recent years, artificial intelligence (AI) technology has proliferated rapidly and widely into application areas such as speech recognition, health care, and autonomous driving. To increase the capabilities of AI more powerful systems are needed t
Publikováno v:
IEEE Access, Vol 6, Pp 31387-31398 (2018)
Computer servers are equipped with an increasing number of memory modules each with more capacity, making main-memory systems now the second most energy-consuming component trailing only processors in big-memory servers. These big-memory servers and
Publikováno v:
IEEE Computer Architecture Letters. 16:76-79
Memory access latency has significant impact on application performance. Unfortunately, the random access latency of DRAM has been scaling relatively slowly, and often directly affects the critical path of execution, especially for applications with
Autor:
Joonsung Kim, Yu-Hwan Ro, Jaehyung Ahn, Jung Ho Ahn, Jae W. Lee, Jongwook Chung, Jangwoo Kim, John Kim
Publikováno v:
PACT
Ensuring fairness or providing isolation between multiple workloads with different characteristics that are colocated on a single, shared-memory system is a challenge. Recent multicore processors provide last-level cache (LLC) hardware partitioning t
Publikováno v:
IISWC
As servers are equipped with more memory modules each with larger capacity, main-memory systems are now the second highest energy-consuming component in big-memory servers and their energy consumption even becomes comparable to processors in some ser
Publikováno v:
HPCA
Memory access latency has a significant impact on application performance. Unfortunately, the random access latency of DRAM has been scaling relatively slowly, and often directly affects the critical path of execution, especially for applications wit
Publikováno v:
Electronics Letters. 51:1320-1322
Phase change memory (PCM) is a promising candidate for the main memory of future computer systems due to its merits such as high capacity and low standby power. However, its poor write performance is a critical issue for it to be fully adopted as mai
Publikováno v:
Electronics
Volume 7
Issue 8
Electronics, Vol 7, Iss 8, p 130 (2018)
Volume 7
Issue 8
Electronics, Vol 7, Iss 8, p 130 (2018)
Following trends that emphasize neural networks for machine learning, many studies regarding computing systems have focused on accelerating deep neural networks. These studies often propose utilizing the accelerator specialized in a neural network an
Autor:
Hye-Jin Kim, Won-Ryul Chung, Sang-beom Kang, Chang-han Choi, Yong-Jin Yoon, Mu-Hui Park, Yu-Hwan Ro, Woo-Yeong Cho, Ki-Sung Kim, Young-Ran Kim, Chang-Hyun Kim, Du-Eung Kim, Beak-Hyung Cho, Byung-Gil Choi, Joon-Min Park, Hongsik Jeong, Kwang-Suk Yu, In-Cheol Shin, Kwang-Jin Lee, Chang-Soo Lee, Gitae Jeong, Choong-keun Kwak, Ki-won Lim, Qi Wang, Joon-Yong Choi, Kinam Kim, Hyung-Rok Oh, Ho-Keun Cho
Publikováno v:
IEEE Journal of Solid-State Circuits. 43:150-162
A 512 Mb diode-switch PRAM has been developed in a 90 nm CMOS technology. The vertical diode-switch using the SEG technology has achieved minimum cell size and disturbance-free core operation. A core configuration, read/write circuit techniques, and