Výsledky vyhledávání - "Young-Ryeol Choi"

Dual-Loop Two-Step ZQ Calibration for Dynamic Voltage–Frequency Scaling in LPDDR4 SDRAM

Publikováno v: IEEE Journal of Solid-State Circuits. 53:2906-2916

This paper presents a dual-loop two-step ZQ calibration scheme with a 20-nm DRAM process to support dedicated supply voltages ( $V_{DD}$ and $V_{DDQ}$ ). The proposed calibration scheme improves system signal integrity by maintaining the targeted out

Externí odkaz: https://explore.openaire.eu/search/publication?articleId=doi_________::357e219db9060554f370c477b6da0d04
https://doi.org/10.1109/jssc.2018.2850937

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A 3.2 Gbps/pin 8 Gbit 1.0 V LPDDR4 SDRAM With Integrated ECC Engine for Sub-1 V DRAM Core Operation

Publikováno v: IEEE Journal of Solid-State Circuits. 50:178-190

A 1.0 V 8 Gbit LPDDR4 SDRAM with 3.2 Gbps/pin speed and integrated ECC engine for sub-1 V DRAM core is presented. DRAM internal read-modify-write operation for data masked write makes the integrated ECC engine possible in a commodity DRAM. Time inter

Externí odkaz: https://explore.openaire.eu/search/publication?articleId=doi_________::b85aa5494f6f90794f6e13df897888c5
https://doi.org/10.1109/jssc.2014.2353799

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Dual-loop 2-step ZQ calibration for dedicated power supply voltage in LPDDR4 SDRAM

Publikováno v: A-SSCC

This paper presents a dual-loop 2-step ZQ calibration scheme with 20nm DRAM process to support dedicated supply voltage (VDD, VDDQ). The proposed calibration scheme maintains a target value of on-die termination (ODT) in DQ/CA regardless of the suppl

Externí odkaz: https://explore.openaire.eu/search/publication?articleId=doi_________::49e6cc5f556a1c86f0e956ef3176bfec
https://doi.org/10.1109/asscc.2017.8240239

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A 40nm 2Gb 7Gb/s/pin GDDR5 SDRAM with a programmable DQ ordering crosstalk equalizer and adjustable clock-tracking BW

Publikováno v: ISSCC

Most DRAM interfaces such as GDDR5 and DDR3 use parallel single-ended signaling due to pin-count restriction and backward compatibility. Notwithstanding poor signal and power integrity issues, GDDR5 speed reached beyond 5Gb/s in recent years by utili

Externí odkaz: https://explore.openaire.eu/search/publication?articleId=doi_________::17f134797a9a27620a368d25d78b0da6
https://doi.org/10.1109/isscc.2011.5746414

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A 7Gb/s/pin GDDR5 SDRAM with 2.5ns bank-to-bank active time and no bank-group restriction

Publikováno v: 2010 IEEE International Solid-State Circuits Conference - (ISSCC).

Externí odkaz: https://explore.openaire.eu/search/publication?articleId=doi_________::6cc843d5d0e2c1ef2d41021d7b3bedcf
https://doi.org/10.1109/isscc.2010.5433889

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Conference

A 40nm 2Gb 7Gb/s/pin GDDR5 SDRAM with a programmable DQ ordering crosstalk equalizer and adjustable clock-tracking BW.

Publikováno v: 2011 IEEE International Solid-State Circuits Conference Digest of Technical Papers (ISSCC); 2011, p498-500, 3p

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