Zobrazeno 1 - 10
of 21
pro vyhledávání: '"Young-Ho Gong"'
Publikováno v:
IEEE Access, Vol 12, Pp 100366-100376 (2024)
As DRAM cells continue to shrink, the conventional single error correction and double error detection (SECDED) code is not sufficient to provide DRAM error resilience. To satisfy DRAM reliability demands, various studies have proposed multi-bit error
Externí odkaz:
https://doaj.org/article/632e0f08566e4e528ebaed313af6ddec
Autor:
Jaehoon Chung, HyunMi Kim, Kyoungseon Shin, Chun-Gi Lyuh, Yong Cheol Peter Cho, Jinho Han, Youngsu Kwon, Young-Ho Gong, Sung Woo Chung
Publikováno v:
ETRI Journal, Vol 44, Iss 5, Pp 849-858 (2022)
Dynamic voltage frequency scaling (DVFS) has been widely adopted for runtime power management of various processing units. In the case of neural processing units (NPUs), power management of neural network applications is required to adjust the freque
Externí odkaz:
https://doaj.org/article/7019db6b66c447488c26803a9450cb76
Autor:
Young-Ho Gong
Publikováno v:
Micromachines, Vol 14, Iss 9, p 1714 (2023)
Personalized PageRank (PPR) is a widely used graph processing algorithm used to calculate the importance of source nodes in a graph. Generally, PPR is executed by using a high-performance microprocessor of a server, but it needs to be executed on edg
Externí odkaz:
https://doaj.org/article/954b76e12c2044d78eaa3a4c25ff1c99
Autor:
Young-Ho Gong
Publikováno v:
IEEE Access, Vol 9, Pp 18915-18926 (2021)
Monolithic 3D (M3D) integration has been emerged as a promising technology for fine-grained 3D stacking. As the M3D integration offers extremely small dimension of via in a nanometer-scale, it is beneficial for small microarchitectural blocks such as
Externí odkaz:
https://doaj.org/article/f12d3c595142442abfabd24a19fa8c66
Autor:
Ji Heon Lee, Young Seo Lee, Jeong Hwan Choi, Hussam Amrouch, Joonho Kong, Young-Ho Gong, Sung Woo Chung
Publikováno v:
IEEE Access, Vol 9, Pp 120715-120729 (2021)
Monolithic 3D (M3D) integration reduces the wire length, which eventually improves energy efficiency and performance compared to 2D integration. However, 3D integration inevitably causes higher on-chip temperature compared to 2D integration due to th
Externí odkaz:
https://doaj.org/article/20989edb02404bf5b3bc606e07969682
Publikováno v:
IEEE Embedded Systems Letters. 13:162-165
Layer-wise quantized neural networks (QNNs), which adopt different precisions for weights or activations in a layer-wise manner, have emerged as a promising approach for embedded systems. The layer-wise QNNs deploy only required number of data bits f
Autor:
Joonho Kong, Ji Heon Lee, Young-Ho Gong, Hussam Amrouch, Young Seo Lee, Sung Woo Chung, Jeong Hwan Choi
Publikováno v:
IEEE Access, Vol 9, Pp 120715-120729 (2021)
Monolithic 3D (M3D) integration reduces the wire length, which eventually improves energy efficiency and performance compared to 2D integration. However, 3D integration inevitably causes higher on-chip temperature compared to 2D integration due to th
Publikováno v:
Integration. 76:183-189
The monolithic 3D stacking (M3D) reduces the critical path delay, leveraging 1) short latency of a monolithic inter-tier via (MIV) and 2) short 2D interconnect and cell delay through smaller footprint. In this paper, we propose M3D stacked multiply-a
Publikováno v:
2022 Design, Automation & Test in Europe Conference & Exhibition (DATE).
Publikováno v:
Journal of Systems Architecture. 134:102787