A 210-mW Graphics LSI Implementing Full 3-D Pipeline With 264 Mtexels/s Texturing for Mobile Multimedia Applications

Autor: Sungwon Shin, Sung-Eun Kim, Sungdae Choi, Hoi-Jun Yoo, Chi-Weon Yoon, Jin-Yong Chung, Kyung-Dong Yoo, Jeong-Ho Woo, In-Cheol Park, Ramchan Woo, Byeong-Gyu Nam, Seong-Jun Song, Ju-Ho Sohn, Young-Don Bae

Publikováno v: IEEE Journal of Solid-State Circuits. 39:358-367

A 121-mm/sup 2/ graphics LSI is designed and implemented for portable two-dimensional (2-D) and three-dimensional (3-D) graphics and MPEG-4 applications. The LSI contains a RISC processor with a multiply-accumulate unit (MAC), a 3-D rendering engine,

Externí odkaz: https://explore.openaire.eu/search/publication?articleId=doi_________::30a505784b0c10f57ad88ae097f10575
https://doi.org/10.1109/jssc.2003.821781

A single-chip programmable platform based on a multithreaded processor and configurable logic clusters

Autor: Seong-Il Park, In-Cheol Park, Yongseok Yi, Young-Don Bae

Publikováno v: 2002 IEEE International Solid-State Circuits Conference. Digest of Technical Papers (Cat. No.02CH37315).

This paper presents a single-chip programmable platform that integrates most of hardware blocks required in the design of embedded system chips. The platform includes a 32-bit multithreaded RISC processor (MT-RISC), configurable logic clusters (CLCs)

Externí odkaz: https://explore.openaire.eu/search/publication?articleId=doi_dedup___::796060a9f360cffd133e938a22a0d867
https://doi.org/10.1109/isscc.2002.992248

A 4.75GOPS single-chip programmable processor array consisting of a multithreaded processor and multiple SIMD and IO processors

Autor: Young-Don Bae, In-Cheol Park

Publikováno v: CICC

This paper describes a configurable platform chip integrating 9 heterogeneous processors, which is designed to enable rapid prototyping and verification without translating functional behaviors into hardware blocks. The chip consists of a 32-bit mult

Externí odkaz: https://explore.openaire.eu/search/publication?articleId=doi_________::5b9dbdd169e34df36031a1fda040e121
https://doi.org/10.1109/cicc.2004.1358891

A 80/20 MHz 160 mW multimedia processor integrated with embedded DRAM MPEG-4 accelerator and 3D rendering engine for mobile applications

Autor: null Chi-Weon Yoon, R. Woo, null Jeonghoon Kook, null Se-Joong Lee, null Langmin Lee, null Young-Don Bae, null In-Cheol Park, null Hoi-Jun Yoo

Publikováno v: 2001 IEEE International Solid-State Circuits Conference. Digest of Technical Papers. ISSCC (Cat. No.01CH37177).

Externí odkaz: https://explore.openaire.eu/search/publication?articleId=doi_________::0a5167c6c271282c2a780a5ea75f2170
https://doi.org/10.1109/isscc.2001.912578

A Low-Power 3-D Rendering Engine With Two Texture Unit and 29-Mb Embedded DRAM for 3G Multimedia Terminals.

Autor: Ramchan Woo, Sungdae Choi, Ju-Ho Sohn, Seong-Jun Song, Young-Don Bae, Hoi-Jun Yoo

Publikováno v: IEEE Journal of Solid-State Circuits; Jul2004, Vol. 39 Issue 7, p1101-1109, 9p, 9 Black and White Photographs, 9 Diagrams, 1 Chart, 5 Graphs